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Display Subsystem Functional Description
7.4.4.4
DSI PLL Controller Shadowing Mechanism
The configuration registers are accessed through the DSI protocol engine register space using SCP port.
This includes all the configuration signals and the returning status signals.
CAUTION
All writes must be 32-bit operations as the SCP always transfers 32 bits. Any
16-bit or 8-bit operations may lead to unpredictable errors.
A shadow mechanism is implemented for appropriate register values so that configurations may optionally
be updated in synchronism with the display controller (DISPC) and DSI protocol engine. The front porch
time from the DISPC indicates the time when making the update of the value. All the required updated
values must have been written before this signal is asserted. See
for more details.
7.4.4.5
Error Handling
The PLL lock and recalibration signals may be monitored to detect loss of lock or requirement to
recalibrate (due to large temperature change since the last lock request):
•
The DSS.
[1] DSI_PLL_LOCK status bit gives the DSI PLL lock state.
•
The DSS.
[2] DSI_PLL_RECAL status bit informs if the PLL must be uncalibrated
These signals can also generate interrupts at DSI protocol engine level:
•
The PLL_LOCK_IRQ interrupt indicates that the DSI PLL control module has sent a lock request to the
DSI PLL. To monitor this event, read the DSS.
[7] PLL_LOCK_IRQ bit. Set this bit to
1 to clear the status bit.
•
The PLL_UNLOCK_IRQ interrupt indicates that the DSI PLL control module has sent an unlock
request to the DSI PLL. To monitor this event, read the DSS.
[8] PLL_UNLOCK_IRQ
bit. Set this bit to 1 to clear the status bit.
•
The PLL_RECAL_IRQ interrupt indicates that the DSI PLL control module has sent a recalibration
request to the DSI PLL. To monitor this event, read the DSS.
[9] PLL_RECAL_IRQ
bit. Set this bit to 1 to clear the status bit.
7.4.5 DSI Complex I/O Functionalities
7.4.5.1
DSI Complex I/O Overview
DSI_PHY is a complex I/O with 3 unidirectional (HS) Lane Modules. This includes 2 data lane modules
and 1 clock lane module. Each lane module has 2 data pads (DX, DY). These data pads are connected
with a complementary lane module on the DSI receiver device using point to point interconnect.
Lane modules support high-speed burst mode. Forward direction and reverse direction escape modes are
also supported. Escape modes maybe used for Low Power Data Transmission, among other things.
The maximum data rate supported is 900 Mbps per data lane. The lane module function and position is
configurable, that is, any lane module can be chosen as clock lane module, and DX/DY data pad for each
lane module can be configured as either DP or DN pins defined by DSI_PHY spec.
DSI_PHY interacts with the higher layers of the DSI link through the PHY-Protocol Interface (PPI).
DSI_PHY does not include a PLL; a high frequency clock input is expected in HS mode (CLKIN4DDR).
DSI_PHY supports also Serial Configuration Protocol (SCP) to set various configuration and control
registers. The DSI_PHY supports GPIO operation on each of the six data pins.
7.4.6 RFBI Functionalities
The RFBI module can capture the output pixel from the display controller and send the data to the RFB in
the LCD panel. The application configures the RFBI module, sends commands, reads data, and
configures the display controller to send data fetched from the system memory by the display controller
DMA engine. The commands/data are sent using an 8-, 9-, 12-, or 16-bit parallel interface.
1687
SWPU177N – December 2009 – Revised November 2010
Display Subsystem
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