Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 1805 / 3738

dss-E126
= -
= ´
=
Re gM4 FCLKIN4DDR / FDSI _ PLL _ REFCLK 1
FCLKIN4DDR 4 FCLKIN
Re gM4 5
dss-E127
= ´ ´ ´ -
=
Re gM3 ((BPP 2) /(DISPC _ LCD DISPC _ PCD NDL)) 1
Re gM3 15
Public Version
www.ti.com
Display Subsystem Use Cases and Tips
Table 7-102. Reset DSI Modules (continued)
Steps Register/Bit Field/Programming Value
Wait until RESET_DONE = 1. DSI_SYSSTATUS [0] RESET_DONE
7.6.5.1.2.2 Configure DSI PLL
Table 7-103 lists the steps required to configure the DSI PLL.
Table 7-103. Configure DSI PLL
Steps Register/Bit Field/Programming Value
Enable PLL and HSDIVIDER. DSI_CLK_CTRL [31:30] PLL_PWR_CMD 0x2
Wait until PLL_PWR_STATUS = 0x2. DSI_CLK_CTRL [29:28] PLL_PWR_STATUS
Set the REGM4 value (see (1) ). DSI_PLL_CONFIGURATION1 [26:23] DSIPROTO_CLK_DIV 5
Set the REGM3 value (see (2) ). DSI_PLL_CONFIGURATION1 [22:19] DSS_CLOCK_DIV 15
Set the REGN value (see (3) ). DSI_PLL_CONFIGURATION1 [7:1] DSI_PLL_REGN 12
Set the REGM value (see (4) ). DSI_PLL_CONFIGURATION1 [18:8] DSI_PLL_REGM 150
Enable PLL STOPMODE. DSI_PLL_CONFIGURATION1 [0] DSI_PLL_STOPMODE 0x1
Enable PLL reference clock control. DSI_PLL_CONFIGURATION2 [13] DSI_PLL_REFEN 0x1
Enable CLKIN4DDR control. DSI_PLL_CONFIGURATION2 [14] DSI_PHY_CLKINEN 0x1
Enable DSS clock divider. DSI_PLL_CONFIGURATION2 [16] DSS_CLOCK_EN 0x1
DSI_PLL_CONFIGURATION2 [18]
Enable DSI protocol engine clock divider. 0x1
DSI_PROTO_CLOCK_EN
Enable DSI configuration update with
DSI_PLL_CONTROL [0] DSI_PLL_AUTOMODE 0x0
DISPC_UPDATE_SYNC.
Start PLL locking sequence. DSI_PLL_GO [0] DSI_PLL_GO 0x1
Wait until DSI_PLL_GO = 0. DSI_PLL_GO [0] DSI_PLL_GO
Check whether PLL is locked. DSI_PLL_STATUS [1] DSI_PLL_LOCK 0x1
Set the LP mode clock ratio. DSI_CLK_CTRL [12:0] LP_CLK_DIVISOR 0x8
Set L3_ICLK clock to the DSI complex I/O to not
DSI_CLK_CTRL [14] CIO_CLK_ICG 0x1
gated.
Enable the automatic assertion/deassertion of the
DSI_CLK_CTRL [18] HS_AUTO_STOP_ENABLE 0x1
DSIStopClk signal.
Specify that the DSI functional clock is higher
DSI_CLK_CTRL [21] LP_RX_SYNCHRO_ENABLE 0x1
than 30 MHz with a synchronization rising/rising.
Turn on PLL and HSDIVIDER. DSI_CLK_CTRL [31:30] PLL_PWR_CMD 0x2
(1) Calculate the divider value for the DSI protocol engine clock source:
(2) Determine LCD, PCD, and REGM3:
Calculate the divider value for the DSS clock source: Same as Step 3.
(3) Calculate N divider for PLL:
1805 SWPU177N – December 2009 – Revised November 2010 Display Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated