Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 1797 / 3738

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Display Subsystem Use Cases and Tips
Table 7-85. PRCM Registers
Steps Registers Value
Set the divided DPLL value for DSS1. CM_CLKSEL_DSS[4:0] CLKSEL_DSS1 0x9
Disable autoidle mode. CM_AUTOIDLE_DSS[31:0] 0x0
Domain sleep is disabled. CM_SLEEPDEP_DSS[31:0] 0x0
Automatic transition between active and inactive are disabled. CM_CLKSTCTRL_DSS[31:0] 0x0
Enable DSS1, DSS2 and TV clock (DSS1_ALWON_FCLK,
DSS2_ALWON_FCLK and TV_CLK). TV_CLK is only need for correct
CM_FCLKEN_DSS[31:0] 0x7
Reset.
Enable the subsystem interface clock (DSS_L3_ICLK and DSS_L4_ICLK). CM_ICLKEN_DSS[31:0] 0x1
7.6.4.2 Configure DSI, DSI PLL and Complex I/O
7.6.4.2.1 Reset DSI Modules
Table 7-86 lists the steps required to reset the DSI modules.
Table 7-86. Resets
Steps Registers Value
Reset IRQ status. DSI_IRQSTATUS [31:0] 0x0
OCP and functional clock are maintained during wakeup, smart idle, and
DSI_SYSCONFIG [31:0] 0x312
reset DSI.
Wait until RESET_DONE
≠
0. DSI_SYSSTATUS [0] RESET_DONE Read 0x1
7.6.4.2.2 Set Up DSI DPLL
Table 7-87 lists the steps required to configure DSI PLL.
Table 7-87. DSI PLL Configuration Registers
Steps Registers Value
Turn on PLL and HSDIVIDER. DSI_CLK_CTRL [31:30] PLL_PWR_CTRL 0x2
Wait until PLL_PWR_STATUS = 0x2. DSI_CLK_CTRL [29:28] PLL_PWR_STATUS Read 0x2
DSI_PLL_CONFIGURATION1 [26:23]
See the calculation following this table. 5
DSIPROTO_CLK_DIV
DSI_PLL_CONFIGURATION1 [22:19]
See the calculation following this table. 15
DSS_CLOCK_DIV
DSI_PLL_CONFIGURATION1 [18:8]
See the calculation following this table. 150
DSI_PLL_REGM
DSI_PLL_CONFIGURATION1 [7:1]
See calculation following this table. 12
DSI_PLL_REGN
Enable PLLStopMode. DSI_PLL_CONFIGURATION1 [0] 0x1
The DSI protocol engine clock divider, DSS clock divider,
CLKIN4DDR, and PLL reference clock are enabled. PLL
DSI_PLL_CONFIGURATION2 [31:0] 0x5600E
internal reference frequency is between 1.75 and 2.1MHz.
Manual mode DSI_PLL_CONTROL [31:0] 0x0
Request PLL locking sequence. DSI_PLL_GO [0] DSI_PLL_GO 0x1
Read until DSI_PLL_GO = 0 DSI_PLL_GO [0] DSI_PLL_GO Read 0x0
PLL is locked. DSI_PLL_STATUS [1] DSI_PLL_LOCK Read 0x1
Turn on PLL and HSDIVIDER; the DSI functional clock >
30-MHz sync is rising/rising; the DSIStopClk signal is
DSI_CLK_CTRL [31:0] 0x8024 4008
automatically asserted/deasserted; the L3_ICLK clock to the
DSI complex I/O is not gated; and LPCLKDIVISOR = 8
1797 SWPU177N – December 2009 – Revised November 2010 Display Subsystem
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