CLKINP
PCLK
TIGHTPHASELOCK
÷
2
HIGHFREQ
0
1
PHASELOCK
FREQLOCK
(TVALID)
LOCKSEL[1:0]
DCOCLKLDO
ADPLLM
0
1
SYS_CLK
CLKSEL
CLKIN4DDR
(To DSI_PHY)
TIGHTPHASELOCK
0
1
2
3
LOCK
SPARE
DSI PLL controller
Display subsystem
Gating
REFEN
PCLKFREE
camdss-180
Public Version
Display Subsystem Functional Description
www.ti.com
Figure 7-104. DSI PLL Reference Diagram
NOTE: PCLK is inverted as the falling edge is the reference edge and ADPLLM uses positive edge as reference
(F/F should be positive edge clock also).
The DSI PLL clock output corresponds to the CLKIN4DDR clock of the DSI complex I/O module.
The DSI PLL reference clock is the DSI_PLL_REFCLK clock. Depending on the setting in
DSS.
[11] DSI_PLL_CLKSEL bit, the reference clock can be either the
DSS2_ALWON_FCLK provided by the PRCM or the PCLKFREE provided by the DISPC module.
7.4.4.3
DSI PLL Operations
The signals of the DSI PLL configuration operate according to
. The values in the table indicate
the operation when the PLL is not locked.
Table 7-35. DSI PLL Operation Modes When Not Locked
DSI PLL
Stop mode
Stop mode
Idle bypass
Operation Mode
Low power
(1)
Fast Relock
(1)
Mode Description
Output clocks
Output clocks
Selects when PLL
stopped
stopped
and HSDIVIDER
Lowest
Fastest
bypass clocks
power standby
start-up time
are used
DSS.
[0] DSI_PLL_IDLE
0
0
1
DSS.
1
0
1
DSI_PLL_LOWCURRSTBY
DSS.
[0] DSI_PLL_STOPMODE
1
1
X
(1)
Recommended
When locked, the PLL output frequency is: [(2xREGM)/(REGN + 1)]x[CLKin(MHz)/(HI 1)]
where:
•
M multiplier is programmed in DSS.
[18:8] DSI_PLL_REGM bit field.
•
N divider is programmed in DSS.
[7:1] DSI_PLL_REGN bit field.
•
HIGHFREQ divider by 2 is enabled by setting the DSS.
[12]
DSI_PLL_HIGHFREQ bit to 1.
1686
Display Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
