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Display Subsystem Basic Programming Model
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Table 7-68. Recommended Programming Values (continued)
Field Name
Value
Description
DSI_BYPASSEN
0
To use PLL as the clock source. For
small displays it may be possible to use
the DSS functional clock, in which case
this bit must be set to 1
DSI_PHY_CLKINEN
1
Enable CLKIN4DDR
DSI_PLL_REFEN
1
Enable PLL reference
DSI_PLL_HIGHFREQ
0/1
Set to 1 if the clock reference is higher
than 32 MHz (21 MHz if
DSS.
DSI_PLL_REGN = 0)
DSI_PLL_CLKSEL
0/1
Set to 0 to use DSS2_ALWON_FCLK as
the PLL reference or set to 1 to use
PCLKFREE as the PLL reference, in this
case the DISPC must be using
DSS1_ALWON_FCLK.
DSI_PLL_LOCKSEL
0x0
Phase lock criteria to lock the PLL
DSI_PLL_DRIFTGUARDEN
0x0
The RECAL status/interrupt must be
used to decide when to perform a PLL
uncalibration No automatic uncalibration
is performed
DSI_PLL_TIGHTPHASELOCK
0
Normal criteria
DSI_LOWCURRSTDBY
0/1
Set to 0 for fast PLL unlock, but higher
standby current Set to 1 for leakage
level standby current, but longer unlock
time
DSI_PLL_PLLLPMODE
0
Normal operation For smaller display
sizes may be possible to set to 1
DSI_PLL_IDLE
0
PLL active
7.5.6 DSI Complex I/O Basic Programming Model
7.5.6.1
Software Reset
The clock domain using the TxByteClkHS from the DSI complex I/O has a dedicated reset done
information in the DSS.
[29] RESET_DONE bit. The DSS.
[1]
SOFT_RESET bit is used to reset the TxByteClkHS power domain. A dummy read using the SCP
interface to any DSI_PHY register is required after DSI_PHY reset to complete the reset of the DSI
complex I/O.
7.5.6.2
Reset-Done Bits
The DSI complex I/O has several clock domains. The reset status for each clock domain is provided in
DSS.
register:
•
DSS.
[31] RESETDONETXBYTECLK bit : Reset done for the TXBYTECLK
domain.
•
DSS.
[26:24] RESETDONETXCLKESCi bits: Reset done for the TXCLKESC
domain for lane i (i between 0 and 2).
•
DSS.
[30] RESETDONESCPCLK bit: Reset done for the SCP clock domain.
Software users must perform a dummy read on this bit to initiate the reset sequence of the SCP finite
state machine. When the reset sequence is complete, the RESETDONESCPCLK signal goes high and
software users can read again the DSS.
[30] RESETDONESCPCLK bit to
ensure that the value is now 1.
NOTE:
Software must not write in the DSI_PHY_SCP registers before the
[30] RESETDONESCPCLK bit is set to 1.
1758
Display Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
