Public Version
Display Subsystem Register Manual
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Bits
Field Name
Description
Type
Reset
1
LANE2_ULPS_
Enables the ULPS for the lane #2. The HW must change the state of the
RW
0x0
SIG1
lane to ULPS only when it is in stop state and there is no data pending
inside the DSI protocol engine and the DSI protocol engine has control of
the bus (BTA has not been sent).
The state of the signal TxULPSExit is changed if lane #3 is a clock lane.
There will be a latency depending on the frequency of TxClkExc. This bit
should be read back to confirm a write has been effective.
0x0: READ: Inactive state effective
WRITE: Request to change to inactive state
0x1: READ: ACTIVE state effective
WRITE: Change request to active. If the lane is a data lane,
TxRequestEsc is asserted and synchronously TxUlpsEsc is asserted for
one period of TxClkEsc.
0
LANE1_ULPS_
Enables the ULPS for the lane #1. The HW must change the state of the
RW
0x0
SIG1
lane to ULPS only when it is in stop state and there is no data pending
inside the DSI protocol engine and the DSI protocol engine has control of
the bus (BTA has not been sent).
The state of the signal TxULPSExit is changed if lane #3 is a clock lane.
There will be a latency depending on the frequency of TxClkExc. This bit
should be read back to confirm a write has been effective.
0x0: READ: Inactive state effective
WRITE: Request to change to inactive state
0x1: READ: ACTIVE state effective
WRITE: Change request to active. If the lane is a data lane,
TxRequestEsc is asserted and synchronously TxUlpsEsc is asserted for
one period of TxClkEsc.
Table 7-405. Register Call Summary for Register DSI_COMPLEXIO_CFG2
Display Subsystem Environment
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Display Subsystem Basic Programming Model
•
•
:
[2] [3] [4] [5] [6] [7] [8] [9]
•
:
[10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27]
Display Subsystem Register Manual
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DSI Protocol Engine Register Mapping Summary
Table 7-406. DSI_RX_FIFO_VC_FULLNESS
Address Offset
0x0000 007C
Physical Address
0x4804 FC7C
Instance
DSI_PROTOCOL_ENGINE
Description
Defines the fullness of each space allocated for each VC.
Type
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
VC3_FIFO_FULLNESS
VC2_FIFO_FULLNESS
VC1_FIFO_FULLNESS
VC0_FIFO_FULLNESS
Bits
Field Name
Description
Type
Reset
31:24
VC3_FIFO_FULLNESS
Fullness of the FIFO allocated for VC 3.The valid values are
R
0x00
from 0 to 127 corresponding to 1x33-bit,...up to 128x33-bit.
23:16
VC2_FIFO_FULLNESS
Fullness of the FIFO allocated for VC 2.The valid values are
R
0x00
from 0 to 127 corresponding to 1x33-bit,...up to 128x33-bit.
15:8
VC1_FIFO_FULLNESS
Fullness of the FIFO allocated for VC 1.The valid values are
R
0x00
from 0 to 127 corresponding to 1x33-bit,...up to 128x33-bit.
7:0
VC0_FIFO_FULLNESS
Fullness of the FIFO allocated for VC 0.The valid values are
R
0x00
from 0 to 127 corresponding to 1x33-bit,...up to 128x33-bit.
1938
Display Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated