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Display Subsystem Basic Programming Model
7.5.4.11 Ultra-Low Power State
This section describes how to enter/exit to/from ultralow-power state (ULPS).
NOTE:
The DSS.
LANEx_ULPS_SIGy bits (x range is 1 to 3
corresponding to lane #1 to lane #3, and y range is 1 to 2) must be read back after writing to
verify that the write operations are effective before proceeding to the next step. This is to
take latency at low TxClkEsc frequencies into account.
7.5.4.11.1 Entering ULPS
To enter into ULPS for a clock lane, the following sequence is required:
1. Wait for DSS.
[17]
LP_BUSY bits to be reset to 0 and ensure that the DSS.
[13] DDR_CLK_ALWAYS_ON
bit is 0.
2. TxUlpsClk state changes from inactive to active by setting the DSS.
LANEx_ULPS_SIG2 (x range is 1 to 3 corresponding to lane #1 to lane #3) bit to 1.
To enter into ULPS for a data lane, the following sequence is required:
1. Wait for all TX_FIFOs for all VCs working in HS are empty, for video mode is not active, and for
DSS.
[16] HS_BUSY bit is reset to 0 (in addition for data lane #1,
DSS.
[17] LP_BUSY bit is reset to 0)
2. TxRequestEsc state changes from inactive to active by setting the DSS.
.
LANEx_ULPS_SIG2 (x range is 1 to 3 corresponding to lane #1 to lane #3) bit to 1.
NOTE:
When the DSS.
LANEx_ULPS_SIG2 and
LANEx_ULPS_SIG1 bits are both being written to 0, they can
be combined into one write. Both bits must be read back to confirm they are effective before
proceeding.
7.5.4.11.2 Exiting ULPS
To exit from ULPS for a clock lane, the following sequence is required:
1. Change the state of TxUlpsExit for each lane to ACTIVE by setting the DSS.
LANEx_ULPS_SIG1 (x range is 1 to 3 corresponding to lane #1 to lane #3) bit to 1.
2. Wait for the ULPSACTIVENOT_ALL1_IRQ interrupt indicating that all lanes with TxUlpsExit active
have acknowledged by asserting UlpsActiveNot. This is performed by monitoring the
DSS.
[31] ULPSACTIVENOT_ALL1_IRQ status bit.
3. Start the wake-up timer (GPTimer).
4. Wait for the time-out.
5. Change TxUlpsClk signals to INACTIVE state for the clock lane by resetting the
DSS.
LANEx_ULPS_SIG2 (x range is 1 to 3 corresponding to lane #1 to lane
#3) bit to 0.
6. Reset the DSS.
LANEx_ULPS_SIG1 (x range is 1 to 3 corresponding to lane
#1 to lane #3) bit to 0.
NOTE:
When the DSS.
LANEx_ULPS_SIG2 and
LANEx_ULPS_SIG1 bits are both being written to 0, they can
be combined into one write. Both bits must be read back to confirm they are effective before
proceeding.
To exit from ULPS for a clock lane, in case ComplexIO is in OFF state (the DSI protocol engine sends
ComplexIO to OFF state by setting DSS.
[28:27] PWROFF = 0x0), the sequence
is:
1747
SWPU177N – December 2009 – Revised November 2010
Display Subsystem
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