CompuLab CL-SOM-AM57 Series Reference Manual Download

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CL-SOM-AM57x

Reference Guide

Summary of Contents for CL-SOM-AM57 Series

Page 1: ...CL SOM AM57x Reference Guide ...

Page 2: ...ion contained in this publication To the extent permitted by law no liability including liability to any person by reason of negligence will be accepted by Compulab Ltd its subsidiaries or employees for any direct or indirect loss or damage caused by omissions from or inaccuracies in this document Compulab Ltd reserves the right to change details in this publication without notice Product and comp...

Page 3: ...rage 14 4 PERIPHERAL INTERFACES 15 4 1 Display Interface 17 4 1 1 Parallel Display interface 17 4 1 2 HDMI Interface 18 4 1 3 LVDS Display interface 18 4 2 Parallel Camera Interface 19 4 3 PCI Express 26 4 4 SATA 27 4 5 USB 3 0 27 4 6 USB2 0 ports 28 4 7 Ethernet 29 4 8 Wireless Interfaces 30 4 8 1 WLAN Only 30 4 8 2 Dual Band WLAN Bluetooth 31 4 9 Analog Audio 31 4 10 Digital Audio McASP 33 4 11 ...

Page 4: ...0 5 2 3 Flash Write protection 51 5 3 Reset 51 5 4 Boot Sequence 51 5 5 Signal Multiplexing Characteristics 53 5 6 RTC 63 5 7 LED 63 6 CARRIER BOARD INTERFACE 64 6 1 Connector Pinout 64 6 2 Mechanical Drawings 74 6 3 Heat Spreader and Cooling Solutions 75 6 4 Standoffs Spacers 75 7 OPERATIONAL CHARACTERISTICS 76 7 1 Absolute Maximum Ratings 76 7 2 Recommended Operating Conditions 76 7 3 DC Electri...

Page 5: ...gnals table 4 12 Updated availability limitation on SO DIMM pins 147 149 151 and 157 in table 38 UART9 and table 39 UART10 Mar 2018 4 14 Updated I2C2 Interface Signals 6 1 Updated I2C2 on SO DIMM pin 25 and 31 Updated I2C2 on pins 25 and 31 in attached excel file 4 12 Table 37 Updated UART8 on Pin 11 6 1 Table 68 pins 11 updated Updated UART8 on pin 11 in attached excel file Apr 2018 4 8 2 Updated...

Page 6: ...ease refer to the CompuLab website Ordering information section to decode the CL SOM AM57x part number http www compulab com products computer on modules cl som am57x ti am5728 am5718 system on module ordering 1 3 Related Documents For additional information refer to the documents listed in Table 2 Table 2 Related Documents Document Location CL SOM AM57x Developer Resources http www compulab com A...

Page 7: ...cated graphics acceleration and video processing engines CL SOM AM57x delivers high performance multimedia and image processing capabilities Dual C66x DSP cores and dedicated dual core ARM Cortex M4 IPUs make CL SOM AM57x a powerful platform for image and video processing systems while dual PowerVR SGX544 GPU and IVA HD video sub system enable multimedia demanding applications Delivering a wide ra...

Page 8: ...x UART up to 3x SPI up to 3x eMMC SD SDIO up to 4x I2S McASP up to 2x CAN bus up to 87x GPIOs up to 5x PWM eHRPWM up to 8x Timer PWM up to 2x Capture Interface eCAP up to 1x Quadrature Encoder up to 2x PRU UART up to 2x PRU eCAP up to 1x PRU MII up to 1x PRU Industrial Ethernet up to 28x PRU EGPI up to 32x PRU EGPO up to 3x Video Input ports GPMC MMC2 UART10 MMC4 Optional bypass 4 bit SDIO WLAN BT...

Page 9: ...gle dual channel 32 bit data bus D Storage On board SLC NAND flash 512MB 1GB N On board eMMC flash 4GB 32GB Display and Camera Display Parallel RGB 24 bit up to 1920 x 1200 HDMI 1 4a up to 1920 x 1200 LVDS up to 1920 x 1080 L Touchscreen On board 4 wire resistive touch screen controller I Capacitive touch screen support through SPI and I2C interfaces Camera Up to 3x parallel camera interfaces Netw...

Page 10: ...pending on board configuration and system workload Mechanical Specifications Dimensions 60 x 68 x 5 mm Weight 35 gram Connectors 204 pin SO DIMM edge connector Environmental and Reliability MTTF 200 000 hours Operation temperature case Commercial 0 to 70 C Extended 20 to 70 C Industrial 40 to 85 C Storage temperature 40 to 85 C Relative humidity 10 to 90 operation 05 to 95 storage Shock 50G 20 ms ...

Page 11: ...t RISC processor NEON SIMD Coprocessor and Vector Floating Point VFPv4 per CPU 32 KiB instruction and 32 KiB data level 1 L1 cache per CPU Shared 1 MiB 2 MiB level 2 L2 cache On Chip 512KiB 2 5MiB Shared Memory RAM 48 KiB bootable ROM Up to 2 C66x Floating Point VLIW DSP Image and video accelerator high definition IVA HD subsystem Two ARM Dual Cortex M4 Image Processing Units IPUs Single Dual Core...

Page 12: ...v7 M and Thumb 2 instruction set architecture ISA ARMv6 SIMD and digital signal processor DSP extensions Single cycle MAC Integrated nested vector interrupt controller NVIC Integrated bus matrix Unicache interface Level 2 L2 master interface MIF splitter On chip ROM and banked RAM memory 3 1 3 Display Subsystem The AM57x display subsystem provides the control signals required to interface the devi...

Page 13: ...RUs shared data and instruction memories internal peripheral modules and an interrupt controller INTC The programmable nature of the PRU cores along with their access to pins events and all device resources provides flexibility in implementing fast real time responses specialized data handling operations custom peripheral interfaces and in offloading tasks from the other processor cores of the dev...

Page 14: ...B DDR3 memory capacities are available with C1500D option only 3 2 2 Bootloader Storage CL SOM AM57x is assembled with 2MBytes of SPI NOR flash The SPI NOR flash is used for boot loader and configuration blocks storage 3 2 3 General Purpose Storage CL SOM AM57x is available with optional on board storage designed to store the operating system and user data One of the following storage devices can ...

Page 15: ...gnal name corresponds to the relevant function in cases where the carrier board pin in question is multifunctional Pin The carrier board interface pin number where the discussed signal is available multifunctional pins are denoted with an asterisk Type Signal type see the definition of different signal types below Description Signal description with regards to the interface in question Availabilit...

Page 16: ...U18 Always pulled up to 1 8V on board CL SOM AM57x typ 5KΩ 15KΩ PU33 Always pulled up to 3 3V on board CL SOM AM57x typ 5KΩ 15KΩ PUSUPPLY Always pulled up to 3 8V 5 25V on board CL SOM AM57x typ 5KΩ 15KΩ PD Always pulled down on board CL SOM AM57x typ 5KΩ 15KΩ ...

Page 17: ...s video and multichannel audio CL SOM AM57x provides access to the main LCD output DPI1 referred in Sitara AM57x technical reference manual as VOUT1 The main features of VOUT1 interface are 24 bit parallel CMOS output interface DPI MIPI DPI 2 0 BT 656 or BT 1120 Supporting up to WUXGA 1920 x 1200 with reduced blanking periods For additional details on display subsystem please refer to the Sitara A...

Page 18: ...148 5 MHz pixel clock Please refer to the AM57x Reference manual for additional details The table below summarizes the HDMI interface signals Table 6 HDMI Interface Signals Signal Name Pin Type Description Availability HDMI1_CEC 34 IOD HDMI consumer electronic control Always HDMI1_CEC 56 IOD HDMI consumer electronic control With C1500 HDMI1_CLOCKX 30 ODS HDMI clock differential positive or negativ...

Page 19: ...high impedance when device in SHTDN With C1500D AND L LVDS_P1 45 ODS Differential LVDS data output high impedance when device in SHTDN With C1500D AND L LVDS_P2 51 ODS Differential LVDS data output high impedance when device in SHTDN With C1500D AND L LVDS_P3 57 ODS Differential LVDS data output high impedance when device in SHTDN With C1500D AND L 4 2 Parallel Camera Interface The camera interfac...

Page 20: ... VIN1A_D13 15 I Video Input 1 Port A Data input With C1500 VIN1A_D13 136 I Video Input 1 Port A Data input With C1500 VIN1A_D14 11 I Video Input 1 Port A Data input With C1500 VIN1A_D14 138 I Video Input 1 Port A Data input With C1500 VIN1A_D15 13 I Video Input 1 Port A Data input With C1500 VIN1A_D15 140 I Video Input 1 Port A Data input With C1500 VIN1A_D16 13 I Video Input 1 Port A Data input W...

Page 21: ...a Enable input With C1500 VIN1A_DE0 97 I Video Input 1 Port A Data Enable input With C1500 VIN1A_DE0 104 I Video Input 1 Port A Data Enable input With C1500 VIN1A_FLD0 98 I Video Input 1 Port A Field ID input With C1500 VIN1A_FLD0 197 I Video Input 1 Port A Field ID input With C1500 AND Without A VIN1A_FLD0 98 I Video Input 1 Port A Field ID input With C1500 VIN1A_FLD0 99 I Video Input 1 Port A Fi...

Page 22: ...Input 2 Port A Data input With C1500 VIN2A_D22 120 I Video Input 2 Port A Data input With C1500 VIN2A_D23 9 I Video Input 2 Port A Data input With C1500 VIN2A_D23 122 I Video Input 2 Port A Data input With C1500 VIN2A_D3 144 I Video Input 2 Port A Data input With C1500 VIN2A_D3 174 I Video Input 2 Port A Data input With C1500 VIN2A_D3 91 I Video Input 2 Port A Data input With C1500 VIN2A_D4 146 I ...

Page 23: ...Input 2 Port B Vertical Sync input With C1500 Table 11 Parallel camera VIN3A Interface Signals Signal Name Pin Type Description Availability VIN3A_CLK0 161 I Video Input 3 Port A Clock input With C1500D VIN3A_D0 94 I Video Input 3 Port A Data input With C1500D VIN3A_D1 92 I Video Input 3 Port A Data input With C1500D VIN3A_D10 128 I Video Input 3 Port A Data input With C1500D VIN3A_D11 130 I Video...

Page 24: ..._D18 110 I Video Input 4 Port A Data input With C1500D VIN4A_D18 15 I Video Input 4 Port A Data input With C1500D VIN4A_D19 17 I Video Input 4 Port A Data input With C1500D VIN4A_D19 112 I Video Input 4 Port A Data input With C1500D VIN4A_D2 142 I Video Input 4 Port A Data input With C1500D VIN4A_D2 89 I Video Input 4 Port A Data input With C1500D AND Without E2 VIN4A_D2 162 I Video Input 4 Port A...

Page 25: ...ideo Input 5 Port A Data input With C1500D VIN5A_D12 17 I Video Input 5 Port A Data input With C1500D VIN5A_D13 15 I Video Input 5 Port A Data input With C1500D VIN5A_D14 11 I Video Input 5 Port A Data input With C1500D VIN5A_D15 13 I Video Input 5 Port A Data input With C1500D VIN5A_D2 52 I Video Input 5 Port A Data input With C1500D VIN5A_D3 58 I Video Input 5 Port A Data input With C1500D VIN5A...

Page 26: ...lways LJCB_CLKP 119 IODS PCIe1_PHY PCIe2_PHY shared Reference Clock Input Output Differential Pair positive Always PCIE_RXN0 133 IDS PCIe1_PHY_RX Receive Data Lane 0 negative mapped to PCIe_SS1 only Always PCIE_RXN1 167 IDS PCIe2_PHY_RX Receive Data Lane 1 negative mapped to either PCIe_SS1 dual lane mode or PCIe_SS2 single lane mode With C1500D PCIE_RXN1 184 IDS PCIe2_PHY_RX Receive Data Lane 1 n...

Page 27: ...onal details please refer to chapter 5 5 of this document 4 5 USB 3 0 USB3 0 interface is derived from the Sitara AM57x SuperSpeed SS USB 3 0 Dual Role Device DRD subsystem USB 3 0 DRD subsystem supports following features Integrated SS USB3 0 PHY and HS FS USB2 0 PHY Supports USB Peripheral or Device mode at speeds SS 5Gbps HS FS and LS Supports USB Host mode at speeds SS 5Gbps HS FS and LS USB s...

Page 28: ...AM57x USB 2 0 DRD subsystem R G M I I 0 USB 2 0 HUB HUB PORT 1 HUB PORT 2 HUB PORT 3 TI PORT 2 Hub Upstream Please refer to the AM57x Reference manual for additional details The table below summarizes the USB interface signals Table 17 USB Interface Signals Signal Name Pin Type Description Availability HUB_USB_OCN 162 I Active LOW Overcurrent Condition Detection Input 100K Pull Up onboard SOM AM57...

Page 29: ...e High activity LED driver fixed 2 5V logic 10KΩ Pull Down onboard SOM AM57x With E2 ETH0_LED_LINK10_100 97 IO Active High 10 100 link LED driver fixed 2 5V logic 10KΩ Pull Down onboard SOM AM57x With E2 ETH0_LED_LINK1000 109 IO Active High 1Gbps link LED driver fixed 2 5V logic With E2 ETH0_MDI0N 83 AIO Negative part of 100ohm diff pair 0 With E2 ETH0_MDI0P 85 AIO Positive part of 100ohm diff pai...

Page 30: ...ntenna connector J1 Can be used with any type of 2 4GHz 5 0GHz antenna for WLAN Bluetooth functionality J1 is available with either W or WAB ordering options of CL SOM AM57x Secondary WLAN antenna connector J2 Can be used with any type of 2 4GHz 5 0GHz antenna for Dual Band WLAN functionality J2 is only available with the WAB ordering option of CL SOM AM57x Table 20 J1 J2 U FL connector data Manuf...

Page 31: ... and BLE When populated WL1837MOD is interfaced with the AM57x through the following interfaces AM57x MMC SD SDIO2 interface is used for WLAN data AM57x UART10 and McASP interfaces are employed for Bluetooth and A2DP data Please refer to the AM57x and the Texas Instruments WL1837MOD respective reference manuals for additional details NOTE CL SOM AM57x WiFi 802 11 a b g n and Bluetooth functionalit...

Page 32: ...nput gain 10 15 kΩ 0 dB input gain 20 30 Input capacitance 10 pF Microphone Input to ADC Input signal level 0 dB 1 0 Vrms Signal to noise ratio A weighted 0 dB gain 85 dB Dynamic range A weighted 60 dB full scale input 85 dB Total harmonic distortion 0dB input 0dB gain 60 55 dB Power supply rejection ratio 1 kHz 100 mVp p 50 dB 20Hz 20kHz 100mVp p 45 Programmable gain Boost 1kHz input Rsource 50Ω ...

Page 33: ...als Signal Name Pin Type Description Availability MCASP2_ACLKX 137 IO MCASP2 Transmit Bit Clock I O Always MCASP2_AHCLKX 154 O MCASP2 Transmit High Frequency Master Clock I O Always MCASP2_AXR0 139 IO MCASP2 Transmit Receive Data I O Always MCASP2_AXR1 143 IO MCASP2 Transmit Receive Data I O Always MCASP2_FSX 145 IO MCASP2 Transmit Frame Sync I O Always Table 24 McASP3 Interface Signals Signal Nam...

Page 34: ...esponse sets as defined in the SD Physical Layer specification v3 01 Full compliance with SDIO command response sets and interrupt read wait suspend resume operations as defined in the SD part E1 specification v3 00 Full compliance with SD Host Controller Standard Specification sets as defined in the SD card specification Part A2 v3 00 Built in 1024 byte buffer for read or write Supported SD v3 0 ...

Page 35: ... Without W WAB MMC4_DAT3 149 IO MMC4 data bit 3 Without W WAB MMC4_SDCD 60 I MMC4 Card Detect Always MMC4_SDWP 62 I MMC4 Card Detect Always NOTE Pins denoted with are multifunctional For additional details please refer to chapter 5 5 of this document 4 12 UART CL SOM AM57x provides up to 9 UART ports The functionality is derived from the UART modules integrated into the Sitara AM57x SoC One UART p...

Page 36: ...Infrared transceiver configure shutdown Without W WAB UART3_TXD 111 O UART3 Transmit Data Output Always UART3_TXD 9 O UART3 Transmit Data Output Always UART3_TXD 149 O UART3 Transmit Data Output Without W WAB Table 33 UART4 Interface Signals Signal Name Pin Type Description Availability UART4_RXD 15 I UART4 Receive Data Input Always UART4_RXD 40 I UART4 Receive Data Input Always UART4_TXD 17 O UAR...

Page 37: ... Input Always UART8_RXD 83 I UART8 Receive Data Input Without E2 UART8_RXD 54 I UART8 Receive Data Input Always UART8_TXD 11 O UART8 Transmit Data Output Always UART8_TXD 85 O UART8 Transmit Data Output Without E2 UART8_TXD 56 O UART8 Transmit Data Output Always Table 38 UART9 Interface Signals Signal Name Pin Type Description Availability UART9_CTSN 7 I UART9 clear to send active low Always UART9...

Page 38: ...CS1 161 I O SPI3 Chip Select I O Always SPI3_CS1 52 I O SPI3 Chip Select I O Always SPI3_CS2 106 I O SPI3 Chip Select I O Always SPI3_CS3 76 I O SPI3 Chip Select I O Always SPI3_D0 100 I O SPI3 Data I O Can be configured as either MISO or MOSI Always SPI3_D0 65 I O SPI3 Data I O Can be configured as either MISO or MOSI Always SPI3_D0 15 I O SPI3 Data I O Can be configured as either MISO or MOSI Al...

Page 39: ...rence manual The tables below summarize the I2C interface signals Table 43 I2C2 Interface Signals Signal Name Pin Type Description Availability I2C2_SDA 25 IOD I2C2 Data I O Always I2C2_SCL 31 IOD I2C2 Clock I O Always Table 44 I2C3 Interface Signals Signal Name Pin Type Description Availability I2C3_SCL 43 IOD I2C2 Clock I O Always I2C3_SCL 113 IOD I2C2 Clock I O Always I2C3_SDA 49 IOD I2C2 Data ...

Page 40: ...ntroller The controller is communicating with the AM57x SoC over the QSPI interface The interface supports 4 wire touch panels and is available through the CL SOM AM57x carrier board interface NOTE CL SOM AM57x Resistive touch interface is available only with the I ordering option Please refer to Texas Instruments TSC2046 datasheet for additional details The table below summarizes the resistive to...

Page 41: ...ring fault conditions Supports trip zone allocation of both latched and un latched fault conditions Allows events to trigger both CPU interrupts and start of ADC conversions Support PWM chopping by high frequency carrier signal used for pulse transformer gate drives For additional details on eHRPWM please refer to the Sitara AM57x technical reference manual The table below summarizes the eHRPWM in...

Page 42: ...e is derived from the Sitara AM57x on SoC The eQEP3 module allows effective sensing of wheel rotation parameters such as direction and speed without software intervention The eQEP3 inputs include two pins for quadrature clock mode or direction count mode an index or 0 marker and a strobe input For additional details on eQEP3 please refer to the Sitara AM57x technical reference manual The table bel...

Page 43: ...SS UART please refer to the Sitara AM57x technical reference manual The table below summarizes the PRUSS_UART interface signals Table 54 PRUSS_UART Interface Signals Signal Name Pin Type Description Availability PR1_UART0_CTS_N 106 I UART Clear To Send Always PR1_UART0_RTS_N 108 O UART Ready To Send Always PR1_UART0_RXD 110 I UART Receive Data Always PR1_UART0_TXD 112 O UART Transmit Data Always P...

Page 44: ...t Always PR2_EDIO_DATA_OUT7 76 O ECAT Digital I Os Data Out Always PR2_EDIO_LATCH_IN 126 I ECAT Digital I O Latch In Always PR2_EDIO_SOF 128 O ECAT Digital I O Start of Frame Always NOTE Pins denoted with are multifunctional For additional details please refer to chapter 5 5 of this document 4 21 4 PRU ICSS Enhanced Capture Event Module PRU ICSS eCAP A PRU ICSS eCAP module is available with CL SOM...

Page 45: ...eneral Purpose Input Always PR2_PRU0_GPI8 202 I PRU0 General Purpose Input Always PR2_PRU0_GPI9 134 I PRU0 General Purpose Input Always PR2_PRU0_GPI9 163 I PRU0 General Purpose Input Always PR2_PRU0_GPO0 112 O PRU0 General Purpose Output Always PR2_PRU0_GPO0 49 O PRU0 General Purpose Output Always PR2_PRU0_GPO1 116 O PRU0 General Purpose Output Always PR2_PRU0_GPO1 43 O PRU0 General Purpose Output...

Page 46: ...U1 General Purpose Output Always PR2_PRU1_GPO2 3 O PRU1 General Purpose Output Always PR2_PRU1_GPO20 110 O PRU1 General Purpose Output Always PR2_PRU1_GPO3 117 O PRU1 General Purpose Output Always PR2_PRU1_GPO3 7 O PRU1 General Purpose Output Always PR2_PRU1_GPO4 111 O PRU1 General Purpose Output Always PR2_PRU1_GPO4 9 O PRU1 General Purpose Output Always PR2_PRU1_GPO5 152 O PRU1 General Purpose O...

Page 47: ...nterface Please refer to the AM57x Reference manual for additional details The table below summarizes the GPIO interface signals Table 59 GPIO Interface Signals Signal Name Pin Type Description Availability GPIO1_1 192 I General Purpose Input 10K PD onboard CL SOM AM57x With C1500D GPIO1_14 54 IO General Purpose Input Output I O Always GPIO1_15 56 IO General Purpose Input Output I O Always GPIO1_1...

Page 48: ...7_10 72 IO General Purpose Input Output I O Without I GPIO7_11 181 IO General Purpose Input Output I O Always GPIO7_12 40 IO General Purpose Input Output I O Always GPIO7_13 34 IO General Purpose Input Output I O Always GPIO7_2 52 IO General Purpose Input Output I O Always GPIO7_22 60 IO General Purpose Input Output I O Always GPIO7_23 62 IO General Purpose Input Output I O Always GPIO7_24 157 IO ...

Page 49: ...put I O Always GPIO8_5 118 IO General Purpose Input Output I O Always GPIO8_6 120 IO General Purpose Input Output I O Always GPIO8_7 122 IO General Purpose Input Output I O Always GPIO8_8 124 IO General Purpose Input Output I O Always GPIO8_9 126 IO General Purpose Input Output I O Always NOTE Pins denoted with are multifunctional For additional details please refer to chapter 5 5 of this document...

Page 50: ...s ON request which transitions the CL SOM AM57x from the OFF to the ACTIVE state If PWRON button is pressed low while the device is on a power on interrupt is triggered Keeping this pin signal constantly low more than the long press delay results in system switch off The duration of long press delay can be set by software to either 6 8 10 or 12 seconds Always ENABLE1 198 SPD Peripheral power reque...

Page 51: ... in the device Generally occurs when the device powers up or an abnormal operation is detected Warm reset is also a global reset but it occurs when the device is in normal operating state and does not affect all the modules in the device This is often done to speed up reset recovery time Warm reset events include software triggered reset per power domain watchdog time out externally triggered via ...

Page 52: ...he initial software from the external SD card CL SOM AM57x will fall back and try to load the initial software from the onboard SPI flash The initial logic value of ALT_BOOT signal defines which of the supported boot sequences is used by the system Table 65 Alternative Boot selection signal Signal Name Pin Type Description Availability ALT_BOOT 185 I PD Active high alternate boot sequence select i...

Page 53: ... Driver off C1500D 3 mcasp5_fsx mcasp5_fsr spi4_d1 uart9_txd i2c5_scl vout2_d21 vin2a_d21 vin1a_d21 vin1a_d10 vin1a_d10 pr2_pru1_gpi2 pr2_pru1_gpo2 Driver off C1500 5 mcasp5_aclkx mcasp5_aclk r spi4_sclk uart9_rxd i2c5_sda vout2_d20 vin4a_d20 vin5a_d11 I vin5a_d11 pr2_pru1_gpi1 pr2_pru1_gpo1 Driver off C1500D 5 mcasp5_aclkx mcasp5_aclk r spi4_sclk uart9_rxd i2c5_sda vout2_d20 vin2a_d20 vin1a_d20 v...

Page 54: ... hdmi1_hp d gpio7_12 Driver off Always 42 hdmi1_data1x Always 43 gpio6_11 mdio_d i2c3_scl vin2b_vsync 1 vin5a_de0 I vin5a_de0 ehrpwm2B pr2_mii1_txen pr2_pru0_gpi1 pr2_pru0_gpo1 gpio6_11 Driver off C1500D 43 gpio6_11 mdio_d i2c3_scl vin2b_vsync 2 vin1a_de0 vin1a_de0 ehrpwm2B pr2_mii1_txen pr2_pru0_gpi1 pr2_pru0_gpo1 gpio6_11 Driver off C1500 44 hdmi1_data1y Always 48 hdmi1_data2x Always 49 gpio6_10...

Page 55: ...art9_txd spi4_d1 kbd_row3 I kbd_row3 ehrpwm1A pr1_uart0_rts_ n pr1_edio_data_in4 pr1_edio_data_out 4 gpio4_0 Driver off C1500D 73 vin2a_vsync0 vin2b_vsync 1 vout2_vsync emu9 uart9_txd spi4_d1 kbd_row3 I kbd_row3 ehrpwm1A pr1_uart0_rts_ n pr1_edio_data_in4 pr1_edio_data_out 4 gpio4_0 Driver off C1500 74 vout1_d22 emu18 vin4a_d6 vin3a_d6 obs15 obs31 pr2_edio_data_in6 pr2_edio_data_ out6 pr2_pru0_gpi...

Page 56: ...iver off With C1500D AND Without E2 89 gpmc_a2 vin1a_d18 vout3_d18 vin2a_d2 vin1a_d2 vin1b_d2 uart7_rxd uart5_ctsn gpio7_5 Driver off With C1500 AND Without E2 90 mmc1_dat3 gpio6_26 Driver off Always 91 gpmc_a3 qspi1_cs2 vin3a_d19 vout3_d19 vin4a_d3 vin4b_d3 uart7_txd uart5_rtsn gpio7_6 Driver off With C1500D AND Without E2 91 gpmc_a3 qspi1_cs2 vin1a_d19 vout3_d19 vin2a_d3 vin1a_d3 vin1b_d3 uart7_...

Page 57: ...vin1a_hsync 0 spi3_d0 gpio4_22 Driver off C1500 101 gpmc_a0 vin3a_d16 vout3_d16 vin4a_d0 vin4b_d0 i2c4_scl uart5_rxd gpio7_3 Driver off With C1500D AND Without E2 101 gpmc_a0 vin1a_d16 vout3_d16 vin2a_d0 vin1a_d0 vin1b_d0 i2c4_scl uart5_rxd gpio7_3 gpmc_a26 gpmc_a16 Driver off With C1500 AND Without E2 102 vout1_vsync vin4a_vsync 0 vin3a_vsync 0 spi3_sclk pr2_pru1_gpi17 pr2_pru1_gpo17 gpio4_23 Dri...

Page 58: ...in1a_d20 obs2 obs18 pr1_ecap0_ecap_cap in_apwm_o pr2_pru0_gpi1 pr2_pru0_gpo1 gpio8_4 Driver off C1500 117 uart3_rxd rmii1_crs mii0_rxdv vin2a_d1 vin4b_d1 spi3_sclk pr1_mii0_rxdv pr2_pru1_gpi3 pr2_pru1_gpo3 gpio5_18 Driver off C1500D 117 uart3_rxd rmii1_crs mii0_rxdv vin2a_d1 vin1b_d1 spi3_sclk pr1_mii0_rxdv pr2_pru1_gpi3 pr2_pru1_gpo3 gpio5_18 Driver off C1500 118 vout1_d5 emu7 vin4a_d21 vin3a_d21...

Page 59: ... 137 mcasp2_aclkx vin1a_d7 pr2_mii0_rxd2 pr2_pru0_gpi18 pr2_pru0_gpo18 Driver off C1500 138 vout1_d14 emu13 vin4a_d14 vin3a_d14 obs9 obs25 pr2_uart0_txd pr2_pru0_gpi11 pr2_pru0_gpo11 gpio8_14 Driver off C1500D 138 vout1_d14 emu13 vin2a_d14 vin1a_d14 vin1a_d14 obs9 obs25 pr2_uart0_txd pr2_pru0_gpi11 pr2_pru0_gpo11 gpio8_14 Driver off C1500 139 mcasp2_axr0 vout2_d10 vin4a_d10 Driver off C1500D 139 m...

Page 60: ..._dsr n gpio7_27 Driver off Without W WAB 154 xref_clk1 mcasp2_axr9 mcasp1_axr 5 mcasp2_ahcl kx mcasp6_ahcl kx vin6a_clk0 timer14 pr2_mii1_crs pr2_pru1_gpi6 pr2_pru1_gpo6 gpio6_18 Driver off C1500D 154 xref_clk1 mcasp2_axr9 mcasp1_axr 5 mcasp2_ahcl kx mcasp6_ahcl kx vin1a_clk0 timer14 pr2_mii1_crs pr2_pru1_gpi6 pr2_pru1_gpo6 gpio6_18 Driver off C1500 155 uart2_rxd uart3_ctsn uart3_rctx mmc4_dat0 ua...

Page 61: ...er off C1500D 192 ddr1_odt1 C1500 193 xref_clk2 mcasp2_axr1 0 mcasp1_axr 6 mcasp3_ahcl kx mcasp7_ahcl kx vout2_clk vin4a_clk0 timer15 gpio6_19 Driver off With C1500D AND Without A 193 xref_clk2 mcasp2_axr1 0 mcasp1_axr 6 mcasp3_ahcl kx mcasp7_ahcl kx vout2_clk vin2a_clk0 vin1a_clk0 timer15 gpio6_19 Driver off With C1500 AND Without A 194 mmc3_dat6 spi4_d0 uart10_ctsn vin2b_de1 vin5a_hsync 0 I vin5...

Page 62: ...er pr2_pru0_gpi14 pr2_pru0_gpo14 Driver off With C1500 AND Without A 202 mmc3_dat4 spi4_sclk uart10_rxd vin2b_d1 vin5a_d1 I vin5a_d1 ehrpwm3A pr2_mii1_rxd3 pr2_pru0_gpi8 pr2_pru0_gpo8 gpio1_22 Driver off C1500D 202 mmc3_dat4 spi4_sclk uart10_rxd vin2b_d1 vin1a_d1 vin1a_d1 ehrpwm3A pr2_mii1_rxd3 pr2_pru0_gpi8 pr2_pru0_gpo8 gpio1_22 Driver off C1500 203 mcasp3_fsx mcasp3_fsr mcasp2_axr 13 uart7_txd ...

Page 63: ...an keep the RTC running to maintain clock and time information even if the main supply is not present The backup battery should be connected to the VCC_RTC power input NOTE VCC_RTC must remain valid at all times for proper operation of the on board RTC 5 8 LED The CL SOM AM57x features a single general purpose green LED controlled by GPIO2_5 signal of the AM57x The LED is ON when GPIO2_5 is logic ...

Page 64: ..._D20 VIN5A_D11 MCASP5_ACLKR MCASP5_ACLKX UART9_RXD SPI4_SCLK I2C5_SDA PR2_PRU1_GPI1 PR2_PRU1_GPO1 4 2 4 2 4 2 4 2 4 2 4 10 4 10 4 12 0 4 14 4 21 5 4 21 5 6 ETH1_MDI0N 4 7 7 VIN1A_D22 VIN1A_D9 VIN2A_D22 VIN4A_D22 VIN5A_D9 MCASP5_AXR0 UART3_RXD UART9_CTSN SPI4_D0 PR2_MDIO_MDCLK PR2_MDIO_MDCLK PR2_PRU1_GPI3 PR2_PRU1_GPO3 4 2 4 2 4 2 4 2 4 2 4 10 4 12 4 12 0 4 21 1 4 21 1 4 21 5 4 21 5 8 ETH1_MDI0P 4 ...

Page 65: ...4 7 21 SATA1_TXP0 4 4 22 ETH1_LED_LINK10_100 4 7 23 SATA1_TXN0 4 4 24 ETH1_MDI3N 4 7 25 HDMI1_DDC_SCL I2C2_SDA 4 1 2 4 14 26 ETH1_MDI3P 4 7 27 SATA1_RXP0 4 4 28 VSYS 5 1 29 SATA1_RXN0 4 4 30 HDMI1_CLOCKX 4 1 2 31 HDMI1_DDC_SDA I2C2_SCL 4 1 2 4 14 32 HDMI1_CLOCKY 4 1 2 33 LVDS_CLKN 4 1 3 34 HDMI1_CEC MMC3_SDWP UART4_TXD SPI1_CS3 DCAN2_RX GPIO7_13 4 1 2 4 11 4 12 0 4 15 4 23 35 LVDS_CLKP 4 1 3 36 HD...

Page 66: ...1_CEC SATA1_LED UART8_TXD DCAN1_RX GPIO1_15 4 1 2 04 4 4 12 4 15 4 23 57 LVDS_P3 4 1 3 58 VIN1A_D3 VIN2B_D3 VIN2B_D3 VIN5A_D3 MMC3_DAT2 UART5_CTSN SPI3_CS0 EQEP3_INDEX PR2_MII_MR1_CLK PR2_PRU0_GPI6 PR2_PRU0_GPO6 GPIO7_1 4 2 4 2 4 2 4 2 4 11 4 12 0 4 20 4 21 1 4 21 5 4 21 5 4 23 59 LVDS_N3 4 1 3 60 MMC4_SDCD UART1_RXD GPIO7_22 4 11 4 12 4 23 61 MMC1_SDCD UART6_RXD GPIO6_27 4 11 4 12 4 23 62 MMC4_SD...

Page 67: ...3 75 VIN1A_D7 VIN2B_D7 VIN2B_D7 VIN5A_D7 MMC3_CLK EHRPWM2_TRIPZONE_INPUT PR2_MII1_TXD3 PR2_PRU0_GPI2 PR2_PRU0_GPO2 GPIO6_29 4 2 4 2 4 2 4 2 4 11 4 18 4 21 1 4 21 5 4 21 5 4 23 76 VOUT1_D23 VIN1A_D7 VIN2A_D7 VIN3A_D7 VIN4A_D7 SPI3_CS3 PR2_EDIO_DATA_IN7 PR2_EDIO_DATA_OUT7 PR2_PRU0_GPI20 PR2_PRU0_GPO20 GPIO8_23 4 1 1 4 2 4 2 4 2 4 2 0 4 21 3 4 21 3 4 21 5 4 21 5 4 23 77 VIN1A_D20 VIN1A_D4 VIN2A_D4 VI...

Page 68: ...1 1 4 2 4 2 4 2 4 2 4 12 4 21 3 4 21 3 4 21 5 4 21 5 4 23 93 VIN2A_DE0 VIN2A_DE0 VIN2A_FLD0 VIN2A_FLD0 VIN2B_DE1 VIN2B_DE1 VIN2B_FLD1 VIN2B_FLD1 GPIO3_29 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 23 94 VOUT1_D16 VIN1A_D0 VIN2A_D0 VIN3A_D0 VIN4A_D0 UART7_RXD PR2_EDIO_DATA_IN0 PR2_EDIO_DATA_OUT0 PR2_PRU0_GPI13 PR2_PRU0_GPO13 GPIO8_16 4 1 1 4 2 4 2 4 2 4 2 4 12 4 21 3 4 21 3 4 21 5 4 21 5 4 23 95 VIN1A_CLK0 ...

Page 69: ...RXD SPI3_CS2 PR1_UART0_CTS_N PR2_PRU1_GPI18 PR2_PRU1_GPO18 GPIO8_0 4 1 1 4 2 4 2 4 2 4 2 4 12 0 4 21 2 4 21 5 4 21 5 4 23 107 ETH0_LED_ACT 4 7 108 VOUT1_D1 VIN1A_D17 VIN2A_D17 VIN3A_D17 VIN4A_D17 UART5_TXD PR1_UART0_RTS_N PR2_PRU1_GPI19 PR2_PRU1_GPO19 GPIO8_1 4 1 1 4 2 4 2 4 2 4 2 4 12 4 21 2 4 21 5 4 21 5 4 23 109 ETH0_LED_LINK1000 4 7 110 VOUT1_D2 VIN1A_D18 VIN2A_D18 VIN3A_D18 VIN4A_D18 PR1_UART...

Page 70: ...23 119 LJCB_CLKP 4 3 120 VOUT1_D6 VIN1A_D22 VIN2A_D22 VIN3A_D22 VIN4A_D22 PR2_EDC_LATCH1_IN PR2_PRU0_GPI3 PR2_PRU0_GPO3 GPIO8_6 4 1 1 4 2 4 2 4 2 4 2 4 21 3 4 21 5 4 21 5 4 23 121 LJCB_CLKN 4 3 122 VOUT1_D7 VIN1A_D23 VIN2A_D23 VIN3A_D23 VIN4A_D23 PR2_EDC_SYNC0_OUT PR2_PRU0_GPI4 PR2_PRU0_GPO4 GPIO8_7 4 1 1 4 2 4 2 4 2 4 2 4 21 3 4 21 5 4 21 5 4 23 123 GND 5 1 124 VOUT1_D8 VIN1A_D8 VIN2A_D8 VIN3A_D8...

Page 71: ...10 PR2_PRU0_GPO10 GPIO8_13 4 1 1 4 2 4 2 4 2 4 2 4 21 2 4 21 5 4 21 5 4 23 137 VIN1A_D7 MCASP2_ACLKX PR2_PRU0_GPI18 PR2_PRU0_GPO18 4 2 4 10 4 21 5 4 21 5 138 VOUT1_D14 VIN1A_D14 VIN2A_D14 VIN3A_D14 VIN4A_D14 PR2_UART0_TXD PR2_PRU0_GPI11 PR2_PRU0_GPO11 GPIO8_14 4 1 1 4 2 4 2 4 2 4 2 4 21 2 4 21 5 4 21 5 4 23 139 VIN1A_D10 VIN2A_D10 VIN4A_D10 MCASP2_AXR0 4 2 4 2 4 2 4 10 140 VOUT1_D15 VIN1A_D15 VIN2...

Page 72: ...4 12 4 23 150 VSYS 5 1 151 MMC4_DAT2 UART1_DTRN UART10_RXD UART2_CTSN UART3_RXD GPIO1_16 4 11 4 12 4 12 4 12 4 12 4 23 152 VIN1A_D0 MCASP5_AHCLKX HDQ0 PR2_MII1_COL PR2_PRU1_GPI5 PR2_PRU1_GPO5 TIMER13 GPIO6_17 CLKOUT2 4 2 4 10 4 17 4 21 1 4 21 5 4 21 5 4 22 4 23 5 2 2 153 MMC4_DAT1 UART1_DSRN UART2_TXD UART3_RTSN UART3_SD GPIO7_27 4 11 4 12 4 12 4 12 4 12 4 23 154 VIN1A_CLK0 MCASP2_AHCLKX PR2_MII1_...

Page 73: ...RXD0 PR2_PRU0_GPI11 PR2_PRU0_GPO11 GPIO1_25 4 2 4 2 4 2 4 2 4 11 4 12 0 4 19 4 21 1 4 21 5 4 21 5 4 23 180 RESERVED 181 SATA1_LED SPI1_CS1 GPIO7_11 4 4 0 4 23 182 PCIE_RXP1 USB_RXP0 04 3 4 5 183 VCC_RTC 5 1 184 PCIE_RXN1 USB_RXN0 4 3 4 5 185 ALT_BOOT 5 4 186 VSYS 5 1 187 RESETN 5 3 188 PCIE_TXP1 USB_TXP0 4 3 4 5 189 EEPROM_WP 5 2 3 190 PCIE_TXN1 USB_TXN0 4 3 4 5 191 MICBIAS 4 9 192 GPIO1_1 4 23 19...

Page 74: ...POUT MCASP3_AXR0 UART5_RXD UART7_CTSN PR2_MII1_RXER PR2_PRU0_GPI14 PR2_PRU0_GPO14 4 2 4 9 4 10 4 12 4 12 4 21 1 4 21 5 4 21 5 202 VIN1A_D1 VIN2B_D1 VIN2B_D1 VIN5A_D1 MMC3_DAT4 UART10_RXD SPI4_SCLK EHRPWM3A PR2_MII1_RXD3 PR2_PRU0_GPI8 PR2_PRU0_GPO8 GPIO1_22 PER_PWREN 4 2 4 2 4 2 4 2 4 11 4 12 0 4 18 4 21 1 4 21 5 4 21 5 4 23 5 2 1 203 VIN1A_D2 LHPOUT MCASP3_FSR MCASP3_FSX UART7_TXD PR2_PRU0_GPI13 P...

Page 75: ...sink or an external cooling solution A cooling solution must be provided to ensure that under worst case conditions the temperature on any spot of the heat spreader surface is maintained according to the CL SOM AM57x temperature specifications Various thermal management solutions can be used with the heat spreader including active and passive approaches Documentation and CAD drawings for the CL SO...

Page 76: ...ing Conditions Table 70 Recommended Operating Conditions Parameter Limitations Min Typ Max Unit Main power supply voltage VSYS Normal operation 3 8 5 25 V Backup battery supply voltage VCC_RTC 1 4 5 5 V VBUS input 0 5 0 5 25 V LDOUSB_IN2 LDOUSB regulator input voltage in PMIC 4 3 5 25 V 7 3 DC Electrical Characteristics Table 71 DC Electrical Characteristics Parameter Operating Conditions Min Typ ...

Page 77: ...Temperature Range Options Range Temp Description Commercial 0o to 70o C Sample boards from each batch are tested for the lower and upper temperature limits Individual boards are not tested Extended 20o to 70o C Every board undergoes a short test for the lower limit 20o C qualification Industrial 40o to 85o C Every board is extensively tested for both lower and upper limits and at several midpoints...

Page 78: ...ing components under the CL SOM AM57x module The carrier board interface connector provides 1mm mating height Bear in mind that there are components on the underside of the CL SOM AM57x Refer to the SB SOM AM57x carrier board reference design schematics 8 2 Carrier Board Troubleshooting Using grease solvent and a soft brush clean the contacts of the mating connectors of both the module and the car...

Page 79: ...L SOM AM57x or even damage the module hardware permanently Before every new attempt of activation check that your module is still functional with CompuLab SB SOM AM57x carrier board It is recommended to assemble more than one carrier board for prototyping in order to ease resolution of problems related to specific board assembly 8 3 Ethernet Magnetics Implementation 8 3 1 Magnetics Selection Refer...

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