Texas Instruments OMAP36 Series, Technical Reference Manual

Page: 2370 / 3738

Public Version
SDMA Basic Programming Model
www.ti.com
8. Set the Read start address in the DMA4_CSSAi [31:0] SRC_START_ADRS bit field.
9. Set the Write start address in the DMA4_CDSAi [31:0] DST_START_ADRS bit field.
10. Set FS to 1 and BS to 0 respectively in DMA4_CCRi [5] FS and DMA4_CCRi [18] BS.
11. Set to 1 the channel enable bit DMA4_CCRi [7] EN bit.
• To configure an LCh to transfer one block per DMA request:
1. Set the number of DMA request associated to the current LCH in the DMA4_CCRi [20:19]
SYNCHRO_CONTROL_UPPER and DMA4_CCRi [4:0] SYNCHRO bit field.
2. Set the data type, also referenced as element size (ES), in the DMA4_CSDPi [1:0] DATA_TYPE bit
field.
3. Set the number of element per frame in the DMA4_CENi [23:0] CHANNEL_ELMNT_NBR bit field.
4. Set in the DMA4_CFNi [15:0] CHANNEL_FRAME_NBR bit field the number of frame (transfers), to take
place before the LCH is disabled.
5. Set the Read Port access type (single or burst access) in the DMA4_CSDPi [8:7] SRC_BURST_EN bit
field.
6. Set the Write Port access type (single or burst access) in the DMA4_CSDPi [15:14] DST_BURST_EN
bit field.
7. Set the Read Port addressing mode in the DMA4_CCRi [13:12] SRC_AMODE bit field.
8. Set the Write Port addressing mode in the DMA4_CCRi [15:14] DST_AMODE bit field.
9. Set the Read start address in the DMA4_CSSAi [31:0] SRC_START_ADRS bit field.
10. Set the Write start address in the DMA4_CDSAi [31:0] DST_START_ADRS bit field.
11. Set FS to 0 and BS to 1 respectively in DMA4_CCRi [5] FS and DMA4_CCRi [18] BS.
12. Set to 1 the channel enable bit DMA4_CCRi [7] EN bit.
• To configure an LCh to transfer one packet per DMA request:
1. Set the number of DMA request associated to the current LCH in the DMA4_CCRi [20:19]
SYNCHRO_CONTROL_UPPER and DMA4_CCRi [4:0] SYNCHRO bit field.
2. Set the data type, also referenced as element size (ES), in the DMA4_CSDPi [1:0] DATA_TYPE bit
field.
3. Set the number of elements per packet to transfer: If the packet requestor is in the source, set
DMA4_CCR [24] SEL_SRC_DST_SYNC to 1 and set the packet element number in the DMA4_CSFIi
register and set the addressing mode of source to constant addressing in DMA4_CCRi [13:12]
SRC_AMODE bit field; else, if the packet requestor is in the destination, set the DMA4_CCRi [24]
SEL_SRC_DST_SYNC to 0 and set the packet element number in the DMA4_CDFIi register and set
the addressing mode of destination to constant addressing in DMA4_CCRi [15:14] DST_AMODE bit
field.
4. Set the number of element per frame in the DMA4_CENi [23:0] CHANNEL_ELMNT_NBR bit field.
5. Set in the DMA4_CFNi [15:0] CHANNEL_FRAME_NBR bit field the number of frame (transfers), to take
place before the LCH is disabled.
6. Set the element number in the packet in the DMA4_CSFIi [15:0] PKT_ELNT_NBR, if constant
addressing or post-incremented addressing modes are used in the source side. However, the number
of elements in the packet is set in the
DMA4_CDFIi [15:0] PKT_ELNT_NBR if constant addressing
mode is used in the destination side.
7. Set the Read Port access type (single or burst access) in the DMA4_CSDPi [8:7] SRC_BURST_EN bit
field.
8. Set the Write Port access type (single or burst access) in the DMA4_CSDPi [15:14] DST_BURST_EN
bit field.
9. Set the Read start address in the DMA4_CSSAi [31:0] SRC_START_ADRS bit field.
10. Set the Write start address in the DMA4_CDSAi [31:0] DST_START_ADRS bit field.
11. Set FS to 1 and BS to 1 respectively in DMA4_CCRi [5] FS and DMA4_CCRi [18] BS.
12. Set to 1 the channel enable bit DMA4_CCRi [7] EN bit.
NOTE: It is possible to stop a transfer by disabling the channel. This is done by resetting the
ENABLE bit in the DMA4_CCRi register.
2370 SDMA SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated