Texas Instruments OMAP36 Series, Technical Reference Manual

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High-Speed USB Host Subsystem
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the linestate to transition from SE0 to J, which is detected by the USB host. The register bit is ORed
with a USBTLL module input signal - the connect control can be software (L4-Core interconnect write
access) or hardware (input level). The speed of the connection is determined by the TLLFULLSPEED
bit below.
• USBHOST. TLL_CHANNEL_CONF_i [6] TLLFULLSPEED bit determines the speed (full or low) of the
USB connect to be emulated. The connect enable (controlled as defined above) results in the
pulling-up of either D+ (1 = full speed) or D– (0 = low speed): See
Table 22-50 .
• The 15kOhm pulldowns are implicit: Because they are supposed to be turned on at least on the host
side of the bus, they do not require an additional control.
NOTE: Sideband control and status actions like pullups are included in parallel (that is, nonserial)
standards (UTMI, ULPI), and do not require any custom additions.
Table 22-50. Pullup Enable Emulation in Serial TLL Modes
USBHOST. TLL_CHANNEL_CONF_i Fields Input Signal Resulting TLL Pullup Emulation
TLLFULLSPEED TLLCONNECT USB State D+ Pullup D– Pullup
1 0 Full-speed unconnected Off Off
1 1 Full-speed connected on Off
0 0 Low-speed unconnected Off Off
0 1 Low-speed connected Off On
22.2.4.2.7 Save and Restore
The SAR mechanism can extract the hardware context of the USBTLL module (after all USB activity has
been suspended) before switching off (=save), save it to an external always-on memory, and reinject it
later after the module has been switched on again and reset (=restore) seamlessly for the USB. Part of
that context is composed of the register fields described in the current chapter. The rest of the context is
composed of the buried flip-flops and memories (not accessible by software) like FSM states, buffer
contents, and miscellaneous random logic bits.
The PRCM.PM_PWSTCTRL_CORE[4] SAVEANDRESTORE bit enables the SAR mechanism for the
USBTLL module (see
Chapter 3 , Power, Reset, and Clock Management). When set, the PRCM module
initiates the save and/or the restore sequences at the appropriate time. When not set, the USB host is
treated as a standard module, and the save/restore sequences do not occur.
Table 22-51 lists the USBTLL registers impacted by the SAR context.
NOTE: Because all addresses give access to the same physical register (that is, to the same piece
of context), the ULPI registers with multiple accesses (write, set, clear) are listed only once in
the table.
Table 22-51. USBTLL Registers Impacted by the SAR Context
Register Name Comments on SAR Policy
USBTLL_SYSCONFIG Except the SOFTRESET bit (write-only)
USBTLL_IRQENABLE -
TLL_SHARED_CONF Except the FCLK_REQ bit
TLL_CHANNEL_CONF_i Except the FSLSLINESTATE field
ULPI_FUNCTION_CTRL_i -
ULPI_INTERFACE_CTRL_i -
ULPI_OTG_CTRL_i -
ULPI_USB_INT_EN_RISE_i -
ULPI_USB_INT_EN_FALL_i -
ULPI_USB_INT_STATUS_i -
3280High-Speed USB Host Subsystem and High-Speed USB OTG Controller SWPU177N – December 2009 – Revised November 2010
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