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IVA2.2 Subsystem Basic Programming Model
5.4.4.5.3 Handling Priority
In IVA2.2 local interconnect arbitration, priority of individual bus requests for a DMA transfer over other
DMA- or CPU-initiated bus requests is defined by the event queue to which the event associated with the
transfer is submitted. This can be configured per event queue in the
[2:0] PRIQ0 and
[6:4] PRIQ1 bit fields. By default, event queues 0 and 1 have the same priority (highest
possible priority is 0x0).
CPU bus-requests priority is defined in the IDMA.
[18:16] PRI bit field. By default, the CPU
has the lowest possible priority (0x7).
Typically, this is used to allow transfer-time preemption, so that, for example, bus requests associated with
event queue 1 are served ahead of event queue 1 or CPU requests.
Example:
•
// DMA#0->0x7 (lowest), DMA#1->0x0 (highest), CPU->0x4 (mid)
•
QUEPRI = (QUEPRI & ~0xFF) | 0x07;
•
= (QUEPRI & ~(0xF16)) | 0x4 16;
5.4.4.5.4 Aged Priority
To prevent having a DMA request stalled for a very long time, the IVA2.2 implements an aged priority
scheme (also referred to as an inversion priority scheme) on the DMA ports to change the priority defined
in the
register. This is done by regularly decreasing the priority level (increasing priority in
arbitration) of a stalled request. The interval between two consecutive updates of the priority level is
defined in the
register. By default, the aged priority scheme is disabled
(
=0x0), and arbitration priority is dictated by programmed values in QUEPRI and
5.4.4.5.5 Optimizing 2D Transfers
IVA2.2 EDMA can be configured so that DMA 2D transfers are optimized, allowing for large bursts to be
generated to the SDRAM. This optimization has no effect on transfers issued as 1D transfers to the
physical channels. This is recommended to enable that feature when the sources or destinations of the 2D
transfers are the VRFB (SDRAM tiling structure).
To fully benefit from the optimization and disable MMU page-crossing checks:
•
Large MMU page(s) are defined for the VRFB view(s) (typically 16MB supersection).
•
The user software ensures that a 2D transfer does not span MMU large pages.
With the preceding conditions, use the following settings to use the IVA2.2 2D burst optimization:
•
.DMA2DOPTEN = 1
•
.PAGEXINGEN = 1
NOTE:
The user software must ensure that a 2D transfer never spans MMU page boundaries. The
reason for IVA_SYSC.
.PAGEXINGEN = 1 is to remove the hardware check
mechanism of 2D bursts crossing MMU pages. A 2D burst that spans these boundaries can
lead to undefined behavior. PAGEXINGEN = 0 prevents such situations through hardware.
5.4.4.6
Starting the Transfer
Before starting the transfer, a trigger event must be associated with the logical channel. Three modes
trigger a DMA transfer:
•
Manual trigger (software-synchronized transfers)
•
Hardware trigger (hardware-synchronized transfers)
•
Automatic trigger (automatic on-submission transfer start)
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SWPU177N – December 2009 – Revised November 2010
IVA2.2 Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated
