Texas Instruments OMAP36 Series, Technical Reference Manual

Page: 2042 / 3738

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L3 Interconnect
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Table 9-70. Register Call Summary for Register L3_RT_NETWORK
L3 Interconnect
• Register Target (RT) : [0]
Table 9-71. L3_RT_INITID_READBACK
Address Offset 0x070
Physical Address 0x6800 0070 Instance RT
Description This register is used by initiators to discover their own identity.
Type R
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved INITID
Bits Field Name Description Type Reset
63:8 Reserved Reserved R 0x00000000000000
7:0 INITID Returns initiator ID of core thread that initiated the read R 0x18
Table 9-72. Register Call Summary for Register L3_RT_INITID_READBACK
L3 Interconnect
• Register Target (RT) : [0]
Table 9-73. L3_RT_NETWORK_CONTROL
Address Offset 0x068
Physical Address 0x6800 0078 Instance RT
Description It controls such interconnect wide functions as the timeout base scale and the disabling of fine grained
hardware clock gating.
Type RW
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Reserved Reserved
CLOCK_GATE_DISABLE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved Reserved
TIMEOUT_BASE
2042 Interconnect SWPU177N – December 2009 – Revised November 2010
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