Texas Instruments OMAP36 Series, Technical Reference Manual

Page: 1814 / 3738

Public Version
Display Subsystem Register Manual
www.ti.com
Table 7-119. Display Controller VID1 Register Mapping Summary (continued)
Register Name (n=1 for VID1) Type Register Width Address Offset Display controller VID1
(Bits) Physical
Address
DISPC_VIDn_CONV_COEF2 RW 32 0x138+((n–1)* 0x90) 0x4805 0538
DISPC_VIDn_CONV_COEF3 RW 32 0x13C+((n–1)* 0x90) 0x4805 053C
DISPC_VIDn_CONV_COEF4 RW 32 0x140+((n–1)* 0x90) 0x4805 0540
DISPC_VIDn_FIR_COEF_Vi RW 32 0x1E0+ ((n–1)*0x20) + 0x4805 05E0 + (i* 0x04)
(3)
(i* 0x04)
(3)
DISPC_VIDn_PRELOAD RW 32 0x230+((n–1)* 0x04) 0x4805 0630
7.7.1.4 Display Controller VID2 Register Mapping Summary
Table 7-120. Display Controller VID2 Register Mapping Summary
Register Name (n=2 for VID2) Type Register Width Address Offset Display controller VID2
(Bits) Physical
Address
DISPC_VIDn_BAj RW 32 0x0BC+((n–1)* 0x90) + 0x4805 054C+ (j *0x04)
(1)
(j * 0x04)
(1)
DISPC_VIDn_POSITION RW 32 0x0C4+((n–1)* 0x90) 0x4805 0554
DISPC_VIDn_SIZE RW 32 0x0C8+((n–1)* 0x90) 0x4805 0558
DISPC_VIDn_ATTRIBUTES RW 32 0x0CC+((n–1)* 0x90) 0x4805 055C
DISPC_VIDn_FIFO_THRESHOLD RW 32 0x0D0+((n–1)* 0x90) 0x4805 0560
DISPC_VIDn_FIFO_SIZE_STATUS R 32 0x0D4+((n–1)* 0x90) 0x4805 0564
DISPC_VIDn_ROW_INC RW 32 0x0D8+((n–1)* 0x90) 0x4805 0568
DISPC_VIDn_PIXEL_INC RW 32 0x0DC+((n–1)* 0x90) 0x4805 056C
DISPC_VIDn_FIR RW 32 0x0E0+((n–1)* 0x90) 0x4805 0570
DISPC_VIDn_PICTURE_SIZE RW 32 0x0E4+((n–1)* 0x90) 0x4805 0574
DISPC_VIDn_ACCUl RW 32 0x0E8 + ((n–1)* 0x90) 0x4805 0578 + (l* 0x04)
(2)
+ (l* 0x04)
(2)
DISPC_VIDn_FIR_COEF_Hi RW 32 0x0F0+ ((n–1)* 0x90) + 0x4805 0580 + (i* 0x08)
(3)
(i* 0x08)
(3)
DISPC_VIDn_FIR_COEF_HVi RW 32 0x0F4+ ((n–1)* 0x90) + 0x4805 0584 + (i*0x08)
(3)
(i* 0x08)
(3)
DISPC_VIDn_CONV_COEF0 RW 32 0x130+((n–1)* 0x90) 0x4805 05C0
DISPC_VIDn_CONV_COEF1 RW 32 0x134+((n–1)* 0x90) 0x4805 05C4
DISPC_VIDn_CONV_COEF2 RW 32 0x138+((n–1)* 0x90) 0x4805 05C8
DISPC_VIDn_CONV_COEF3 RW 32 0x13C+((n–1)* 0x90) 0x4805 05CC
DISPC_VIDn_CONV_COEF4 RW 32 0x140+((n–1)* 0x90) 0x4805 05D0
DISPC_VIDn_FIR_COEF_Vi RW 32 0x1E0+ ((n–1)*0x20) + 0x4805 0670 + (i* 0x04)
(3)
(i* 0x04)
(3)
DISPC_VIDn_PRELOAD RW 32 0x230+((n–1)* 0x04) 0x4805 0634
(1)
j = 0 to 1
(2)
l = 0 to 1
(3)
i = 0 to 7
7.7.1.5 RFBI Register Mapping Summary
Table 7-121. RFBI Register Mapping Summary
Register Name Type Register Width Address Offset Physical Address
(Bits)
RFBI_REVISION R 32 0x00 0x4805 0800
RFBI_SYSCONFIG RW 32 0x10 0x4805 0810
1814Display Subsystem SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated