timers-015
M_IRQ_36
nc
MPU
subsystem
PRCM
MPU watchdog timer (WDT2)
WDT2_FCLK
WDT2_CMDRST
WDT2_IRQ
nc
L4
interconnect
MPU_WD_RST
WKUP_32K_FCLK
WDT2_ICLK
WKUP_L4_ICLK
WDT2_RST
WKUP_RST
IVA2 watchdog timer (WDT3)
WDT3_FCLK
WDT3_CMDRST
WDT3_IRQ
L4
interconnect
PER_32K_ALWON_FCLK
WDT3_ICLK
PER_L4_ICLK
WDT3_RST
PER_RST
Public Version
www.ti.com
Watchdog Timers
–
32-/16-bit access supported
–
8-bit access not supported
–
11-bit address bus width
–
Burst mode not supported
–
Write nonposted transaction mode only
•
Free-running 32-bit upward counter
•
Programmable divider clock source (2
n
with n=[0:7])
•
On-the-fly read/write register (while counting)
•
Subset programming model of the GP timer
•
WDTs are reset either on power-on or after a warm reset.
•
Reset or interrupt actions when a timer overflow condition occurs
•
WDT generates either a reset or an interrupt in its hardware integration (WDT2, or WDT3).
16.4.2 WDT Integration
shows the integration of the WDT in the device.
Figure 16-15. WDT Integration
16.4.2.1 Clocking, Reset, and Power-Management Scheme
16.4.2.1.1 Clock Management
There are two clock domains in the WDTs:
•
Functional clock domain: WDTi_FCLK is the WDT functional clock. It is used to clock the WDT internal
logic.
•
Interface clock domain: WDTi_ICLK is the WDT interface clock. It is used to synchronize the WDT L4
port to the L4 interconnect. All accesses from the interconnect are synchronous to WDTi_ICLK.
lists the the source clocks for each WDT in the device. For more information on clock control
and domains, see
, Power, Reset, and Clock Management.
Table 16-57. Clock, Power, and Reset Domains for WDTs
Timer
Interface Clock
Functional Clock
Power Domain
MPU WDT
WKUP_L4_ICLK
WKUP_32K_FCLK
WKUP
IVA2 WDT
PER_L4_ICLK
PER_32K_ALWON_FCLK
PER
2747
SWPU177N – December 2009 – Revised November 2010
Timers
Copyright © 2009–2010, Texas Instruments Incorporated