Texas Instruments OMAP36 Series, Technical Reference Manual

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McBSP Register Manual
Table 21-41. McBSP4 Registers Mapping Summary (continued)
Register Name Type Register Address Offset Physical Address
Width (Bits)
MCBSPLP_PCR_REG RW 32 0x0000 0048 0x4902 6048
MCBSPLP_RCERC_REG RW 32 0x0000 004C 0x4902 604C
MCBSPLP_RCERD_REG RW 32 0x0000 0050 0x4902 6050
MCBSPLP_XCERC_REG RW 32 0x0000 0054 0x4902 6054
MCBSPLP_XCERD_REG RW 32 0x0000 0058 0x4902 6058
MCBSPLP_RCERE_REG RW 32 0x0000 005C 0x4902 605C
MCBSPLP_RCERF_REG RW 32 0x0000 0060 0x4902 6060
MCBSPLP_XCERE_REG RW 32 0x0000 0064 0x4902 6064
MCBSPLP_XCERF_REG RW 32 0x0000 0068 0x4902 6068
MCBSPLP_RCERG_REG RW 32 0x0000 006C 0x4902 606C
MCBSPLP_RCERH_REG RW 32 0x0000 0070 0x4902 6070
MCBSPLP_XCERG_REG RW 32 0x0000 0074 0x4902 6074
MCBSPLP_XCERH_REG RW 32 0x0000 0078 0x4902 6078
MCBSPLP_REV_REG R 32 0x0000 007C 0x4902 607C
MCBSPLP_RINTCLR_REG RW 32 0x0000 0080 0x4902 6080
MCBSPLP_XINTCLR_REG RW 32 0x0000 0084 0x4902 6084
MCBSPLP_ROVFLCLR_REG RW 32 0x0000 0088 0x4902 6088
MCBSPLP_SYSCONFIG_REG RW 32 0x0000 008C 0x4902 608C
MCBSPLP_THRSH2_REG RW 32 0x0000 0090 0x4902 6090
MCBSPLP_THRSH1_REG RW 32 0x0000 0094 0x4902 6094
MCBSPLP_IRQSTATUS_REG RW 32 0x0000 00A0 0x4902 60A0
MCBSPLP_IRQENABLE_REG RW 32 0x0000 00A4 0x4902 60A4
MCBSPLP_WAKEUPEN_REG RW 32 0x0000 00A8 0x4902 60A8
MCBSPLP_XCCR_REG RW 32 0x0000 00AC 0x4902 60AC
MCBSPLP_RCCR_REG RW 32 0x0000 00B0 0x4902 60B0
MCBSPLP_XBUFFSTAT_REG R 32 0x0000 00B4 0x4902 60B4
MCBSPLP_RBUFFSTAT_REG R 32 0x0000 00B8 0x4902 60B8
MCBSPLP_SSELCR_REG RW 32 0x0000 00BC 0x4902 60BC
MCBSPLP_STATUS_REG R 32 0x0000 00C0 0x4902 60C0
21.6.2 SIDETONE Register Mapping Summary
Table 21-42. SIDETONE_McBSP2 Registers Mapping Summary
Register Name Type Register Width (Bits) Address Offset Physical Address
ST_REV_REG R 32 0x0000 0000 0x4902 8000
ST_SYSCONFIG_REG RW 32 0x0000 0010 0x4902 8010
ST_IRQSTATUS_REG RW 32 0x0000 0018 0x4902 8018
ST_IRQENABLE_REG RW 32 0x0000 001C 0x4902 801C
ST_SGAINCR_REG RW 32 0x0000 0024 0x4902 8024
ST_SFIRCR_REG RW 32 0x0000 0028 0x4902 8028
ST_SSELCR_REG RW 32 0x0000 002C 0x4902 802C
Table 21-43. SIDETONE_McBSP3 Registers Mapping Summary
Register Name Type Register Width (Bits) Address Offset Physical Address
ST_REV_REG R 32 0x0000 0000 0x4902 A000
ST_SYSCONFIG_REG RW 32 0x0000 0010 0x4902 A010
3159 SWPU177N – December 2009 – Revised November 2010 Multi-Channel Buffered Serial Port
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