Public Version
MMC/SD/SDIO Overview
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Programmable clock generation
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Support SDIO Read Wait and Suspend/Resume functions
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Support Stop at block gap
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Support command completion signal (CCS) and command completion signal disable (CCSD)
management as specified in the CE-ATA Standard Specification
The known limitations are as follows:
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No built-in hardware support for error correction codes (ECC). See the Multimedia Card System
Specification, v4.2, and the SD Memory Card Specifications, v2.0, for details about ECC.
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The maximum block size defined in the SD Memory Card Specifications, v2.0, that the host driver can
read and write to the buffer in the host controller is 2048 bytes. MMC supports a maximum block size
of 1024 bytes. Up to 512 byte transfers, the buffer in MMC is considered as a double buffering with
ping-pong management; half of the buffer can be written while the other part is read. For 512 to 1024
byte transfers, the entire buffer is dedicated to the transfer (read only or write only).
The differences between the MMC/SD/SDIO host controllers and a Standard SD host controller are
defined by the SD Card Specification, Part A2, SD Host Controller Standard Specification, v1.00, as
follows:
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The MMC/SD/SDIO host controllers support MMC cards.
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The MMC/SD/SDIO host controller is defined as a DMA slave device. Standard SD host controller is
defined as DMA master controller that can start and stop a DMA transfer. MMC/SD/SDIO host
controllers support DMA transfers through slave DMA requests.
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The clock divider in MMC/SD/SDIO host controller supports a wider range of frequency than specified
in the SD Memory Card Specifications, v2.0. The MMC/SD/SDIO host controller supports odd and
even clock ratio.
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The MMC/SD/SDIO host controller supports configurable busy timeout.
3366
MMC/SD/SDIO Card Interface
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated