Texas Instruments OMAP36 Series, Technical Reference Manual

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McBSP Register Manual
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Table 21-53. Register Call Summary for Register MCBSPLP_RCR2_REG
McBSP Environment
• Words, Frames, and Phases Definitions : [0] [1] [2]
McBSP Functional Description
• Bit Reordering (Option to Transfer LSB First) : [3]
• Clocking and Framing Data : [4] [5]
• Frame Phases (Dual-Phase Frame I2S Support) : [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
• McBSP Reception : [16]
• MCBSP Data Transfer Mode : [17]
• Unexpected Receive Frame-sync Pulse : [18]
• Configuring a Frame for Multichannel Selection : [19]
• SIDETONE Interface : [20]
McBSP Basic Programming Model
• McBSP Initialization Procedure : [21]
• Receiver Configuration : [22] [23] [24] [25] [26] [27]
• SIDETONE Activation Procedure : [28]
McBSP Register Manual
• McBSP Register Mapping Summary : [29] [30] [31] [32] [33]
Table 21-54. MCBSPLP_RCR1_REG
Address Offset 0x0000 001C
Physical Address 0x4807 401C Instance McBSP1
0x4809 601C McBSP5
0x4902 201C McBSP2
0x4902 401C McBSP3
0x4902 601C McBSP4
Description McBSPLP receive control register 1
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RFRLEN1 RWDLEN1 RESERVED
Bits Field Name Description Type Reset
31:15 RESERVED Read returns 0x0. R 0x00000
14:8 RFRLEN1 Receive Frame Length 1 RW 0x00
Single-phase frame selected: RFRLEN1=000 0000 - 1
word per frame
RFRLEN1=000 0001 - 2 words per frame
RFRLEN1=111 1111 - 128 words per frame
Dual-phase frame selected: RFRLEN1=000 0000 - 1
word per phase
(other values are reserved)
7:5 RWDLEN1 Receive Word Length 1 RW 0x0
0x0: 8 bits
0x1: 12 bits
0x2: 16 bits
0x3: 20 bits
0x4: 24 bits
0x5: 32 bits
0x6: Reserved (do not use)
0x7: Reserved (do not use)
4:0 RESERVED Read returns 0x0. R 0x00
3166 Multi-Channel Buffered Serial Port SWPU177N – December 2009 – Revised November 2010
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