Texas Instruments OMAP36 Series, Technical Reference Manual

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mcbspi_fsx
mcbspi_dx
Data N
FSX sampled
Data driven
1-bit data delay
Start of the frame
Data N-1
mcbspi_clkx
(configured on rising edge)
mcbsp-069
Public Version
McBSP Functional Description
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During the receive disable state, the frames that are sent (when FSR signal is asserted while receive
disable) by the remote device are lost, and receive buffer overflow status bit
(McBSPi.
MCBSPLP_IRQSTATUS_REG [5] ROVFLSTAT) is not set. Also, the frames received by the
remote device while McBSPi. MCBSPLP_XCCR_REG [0] XDISABLE bit is set (when FSX signal is
asserted while transmit disable) are meaningless undefined data frames, and transmit buffer underflow
status bit (McBSPi.
MCBSPLP_IRQSTATUS_REG [11] XUNDFLSTAT) is not set. The presence of the
frame synchronization, while transmit/receive process is disabled, can be checked by reading the
transmit/receive Frame-sync interrupt status: McBSPi.
MCBSPLP_IRQSTATUS_REG [8] XFSX /
McBSPi. MCBSPLP_IRQSTATUS_REG [1] RFSR bits.
As soon as the McBSPi. MCBSPLP_XCCR_REG [0] XDISABLE/McBSPi. MCBSPLP_RCCR_REG [0]
RDISABLE bit is cleared, the transmit/receive process resumes at the next frame boundary.
NOTE: It is not recommended to use this mechanism together with the possibility to interrogate the
transmit/receive buffer status register (McBSPi. MCBSPLP_XBUFFSTAT_REG [7:0]
XBUFFSTAT/McBSPi. MCBSPLP_RBUFFSTAT_REG [7:0] RBUFFSTAT field indicating the
occupied/available buffer locations), since this register is an interface clock (McBSPi_ICLK)
synchronous register and does not reflect the exact number of occupied/free locations
available on the functional clock domain.
21.4.2.8 MCBSP Data Transfer Mode
NOTE: For all examples in this section, the configured CLKX edge is the rising edge
(McBSPi. MCBSPLP_PCR_REG [1] CLKXP bit=0x0) and the configured CLKR edge is the
falling edge (McBSPi. MCBSPLP_PCR_REG [0] CLKRP bit=0x0). These are the reset values.
In timing diagrams below, a 1-bit data delay is selected
(McBSPi.
MCBSPLP_RCR2_REG [1:0] RDATDLY field=0x01 and
McBSPi. MCBSPLP_XCR2_REG [1:0] XDATDLY field=0x01), because data often follows a
1-cycle active frame-synchronisation.
McBSP modules can support 2 edge selection modes for transmit and receive data transfer at the system
level:
• The full cycle mode, for which one clock period is used to transfer the data, generated on one edge
and captured on the same edge (one clock period later).
• The half cycle mode, for which one half clock period is used to transfer the data, generated on one
edge and captured on the opposite edge (one half clock period later). Note that a new data is
generated only every clock period, which permits to guarantee the required hold time.
21.4.2.8.1 Transmit Full Cycle Mode
When configured in full cycle mode (McBSPi. MCBSPLP_XCCR_REG [11] XFULL_CYCLE bit = 0x1), the
FSX signal is sampled on the configured CLKX edge and the data is driven on the same configured edge.
See
Figure 21-35 .
Figure 21-35. Transmit Full Cycle Timing Diagram
3102 Multi-Channel Buffered Serial Port SWPU177N – December 2009 – Revised November 2010
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