Public Version
McBSP Register Manual
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Table 21-124. MCBSPLP_RCCR_REG
Address Offset
0x0000 00B0
Physical Address
0x4807 40B0
Instance
McBSP1
0x4809 60B0
McBSP5
0x4902 20B0
McBSP2
0x4902 40B0
McBSP3
0x4902 60B0
McBSP4
Description
McBSPLP receive configuration control register
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
RESERVED
RDMAEN
RDISABLE
RESERVED
RFULL_CYCLE
Bits
Field Name
Description
Type
Reset
31:12
RESERVED
Read returns 0x0.
R
0x0000000
11
RFULL_CYCLE
Receive full cycle mode select:
RW
0x1
0x0: McBSP module operates in receive half-cycle mode
(receive frame synchronization is sampled by the
opposite edge of the clock used to sample receive data)
0x1: McBSP module operates in receive full-cycle mode
(receive frame synchronization is sampled by the same
edge of the clock used to sample receive data)
10:4
RESERVED
Read returns 0x0.
R
0x0000000
3
RDMAEN
Receive DMA Enable bit. When set to zero this bit will
RW
0x1
gate the external transmit DMA request, without resetting
the DMA state machine. It is recommended to change
this bit value only during receive reset.
0x0: When set to zero this bit will gate the external
transmit DMA request
0x1: When set to one this bit will NOT gate the external
transmit DMA request
2:1
RESERVED
Read returns 0x0.
R
0x0
0
RDISABLE
Receive Disable bit. When this bit is set the receive
RW
0x0
process will stop at the next frame boundary.
0x0: the receive process will NOT stop at the next frame
boundary.
0x1: When this bit is set the receive process will stop at
the next frame boundary.
Table 21-125. Register Call Summary for Register MCBSPLP_RCCR_REG
McBSP Functional Description
•
Enable/Disable the Transmit and Receive Processes
•
•
McBSP Basic Programming Model
•
:
•
McBSP Register Manual
•
McBSP Register Mapping Summary
:
3200Multi-Channel Buffered Serial Port
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated