CLKX
DX
FSX
For 0-bit delay:
Next frame-sync pulse
here or later is OK.
For 1-bit delay:
Next frame-sync pulse
here or later is OK.
For 2-bit delay:
Next frame-sync pulse
here or later is OK.
Last bit of
current frame
Earliest possible time
to begin transfer of
next frame
mcbsp-041
Public Version
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McBSP Functional Description
Figure 21-46. Proper Positioning of Transmit Frame-sync Pulses
21.4.4.7 Overflow in the Transmitter
The McBSP module indicates a transmitter overflow condition by setting the
McBSPi.
[12] XOVFLSTAT bit. This error occurs when sDMA controller or
MPU/IVA2.2 subsystem write data to a full XB (this may happen only if the MPU/IVA2.2 subsystem or
sDMA controller does not respect the DMA length, does not wait for DMA request or does not check the
buffer status before writing data). According to the McBSPi.
register
settings this condition can generate the McBSPi_IRQ line to be asserted low. Writing 1 to the
corresponding bit in status register clears the interrupt.
21.4.5 McBSP DMA Configuration
The McBSP receive and transmit data DMA requests are active after the receive
McBSPi.
[0] RRST and transmit McBSPi.
[0] XRST are
released. After reset the default DMA threshold (and length) is one.
The receive and transmit DMA requests can be individually disabled by setting the
McBSPi.
[3] RDMAEN, McBSPi.
[3] XDMAEN bits to 0.
When disabling the DMA, the DMA request line is de-asserted even if a DMA transfer is pending and the
DMA state-machine is not reset.
The DMA threshold and length configuration is done through McBSPi.
and
McBSPi.
registers as follows:
•
(THRS 1) value represents the required receive DMA request length (the length of the
transfer is the same as the threshold value plus one). As long as the RB occupied locations level is
above or equal to the THRSH1_REG value + 1, the DMA request is asserted. After transferring the
configured (THRS 1) number of words, the receive DMA request is de-asserted and
reasserted as soon as the conditions are met again.
•
(THRS 1) value represents the required transmit DMA request length (the length of the
transfer is the same as the threshold value plus one). As long as the XB free locations level is above
or equal to the THRSH2_REG value + 1, the DMA request is asserted. After transferring the configured
(THRS 1) number of words, the transmit DMA request is de-asserted and reasserted as
soon as the conditions are met again.
3113
SWPU177N – December 2009 – Revised November 2010
Multi-Channel Buffered Serial Port
Copyright © 2009–2010, Texas Instruments Incorporated