Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 3101 / 3738

Transmit shift
register
(XSR)
DXR_REG
From MPU/IVA2
ss or sDMA
Transmit buffer
(XB)
REVERSE
(LSB first)
mcbspi_dx
mcbsp-032
CLKX
DX
FSX
A1 B7 B6 B5 B4 B3 B2 B1 B0 A0 C7 C6 C5
XRDY
DXR to XB copy (B)
Write to DXR (C)
DXR to XB copy (C)
Write to DXR
XRDY: Status of transmitter ready bit (high is 1)
mcbsp-033
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McBSP Functional Description
6. The MPU/IVA2.2 subsystem or the sDMA controller reads the data from the data receive register.
When the RB is empty, McBSPi. MCBSPLP_SPCR1_REG [1] RRDY bit is cleared.
21.4.2.6 McBSP Transmission
This section explains the fundamental process of transmission in the McBSP module. For details about
how to program the McBSP transmitter, see
Section 21.5 , and Section 21.5.1.6 .
Figures below show how transmission occurs in the McBSP module. A description of the process follows
the figures.
Figure 21-33 shows the physical path for the data.
Figure 21-33. McBSP Transmission Physical Data Path
Figure 21-34 is a timing diagram showing signal activity for one possible transmission scenario.
Figure 21-34. McBSP Transmission Signal Activity
1. The MPU/IVA2.2 subsystem or the sDMA controller writes data to the data transmit register
(McBSPi. MCBSPLP_DXR_REG ). When the XB is reached the transmitter ready bit
(McBSPi. MCBSPLP_SPCR2_REG [1] XRDY bit) is cleared to indicate that the transmitter is not ready
for new data. For details on choosing a word length, see Section 21.5.1.6.2.2.2 .
2. When new data arrives in McBSPi. MCBSPLP_DXR_REG register, the McBSP module copies the
content of the data transmit register to the XB. In addition, the transmit ready bit
(McBSPi.
MCBSPLP_SPCR2_REG [1] XRDY bit) is set as long as the buffer contains at least the
transmit threshold number of free locations (McBSPi. MCBSPLP_THRSH2_REG [10:0] XTHRESHOLD
field). This indicates that the transmitter is ready to accept new data from the MPU/IVA2.2 subsystem
or the sDMA controller.
3. The McBSP module waits for a transmit frame-synchronization pulse on FSX_int.
4. When the pulse arrives, the McBSP module inserts the appropriate data delay that is selected with the
McBSPi. MCBSPLP_XCR2_REG [1:0] XDATDLY field.
In the preceding timing diagram, a 1-bit data delay is selected.
5. The McBSP module shifts data bits from the XSR to the mcbspi_dx pin.
21.4.2.7 Enable/Disable the Transmit and Receive Processes
The McBSP module has the option to stop-resume the transmit/receive process while the module is in
functional mode (out of transmit/receive reset).
When the transmit/receive disable bit (McBSPi. MCBSPLP_XCCR_REG [0]
XDISABLE/McBSPi. MCBSPLP_RCCR_REG [0] RDISABLE) is set, the McBSP module stops the
transmit/receive operation at the next frame boundary (frame corruption avoided).
3101 SWPU177N – December 2009 – Revised November 2010 Multi-Channel Buffered Serial Port
Copyright © 2009–2010, Texas Instruments Incorporated