Receiver
Transmitter
SIDETONE core
CH1 and CH0 channel filter
CH0 Gain
SUM
SUM
Receive Channel CH1
(from Receive Shift Register)
Transmit channel CH 0
(to Transmit Shift Register)
Transmit channel CH1
(to Transmit Shift Register)
CH1 Gain
CH1GAIN (from SGAINCR_REG)
CH0GAIN (from SGAINCR_REG)
Transmit Channel CH 0
(from Transmit Buffer)
Transmit Channel CH1
(from Transmit Buffer)
FIRCOEFF (from SFIRCR_REG)
24
24
24
24
24
24
Receive channel CH0
(from Receive Shift Register)
ST_CH1_DATAR
ST_CH1_DATAX
ST_CH0_DATAR
ST_CH0_DATAX
mcbsp-048
Public Version
www.ti.com
McBSP Functional Description
shows the SIDETONE external module data path:
Figure 21-53. SIDETONE Data Path
Before you enable a SIDETONE selection mode, make sure you properly configure the data frame for
multichannel and SIDETONE mode:
•
Select a single–phase frame (McBSPi.
[15] RPHASE bit and
[15] XPHASE bit=0). Each frame represents a TDM data stream.
•
Set McBSPi.
[0] RMCM=1 to select multichannel mode enable.
•
Set a frame length (in McBSPi.
[14:8] RFRLEN1 bit field and in
[14:8] XFRLEN1 bit field) that includes the highest–numbered channel
to be used (a maximum of 4 channels can be used in this configuration).
•
Set a word length (in McBSPi.
[7:5] RWDLEN1 bit field and in
[7:5] XWDLEN1 bit field) to be either 16, 24 or 32 (see note).
•
Select the input/output channels configured as SIDETONE channels and enable SIDETONE by setting
the McBSPi.
[1:0] ICH0ASSIGN/McBSPi.
[6:4]
OCH0ASSIGN , McBSPi.
[3:2]
[9:7] OCH1ASSIGN fields (2 out of 4 channels
external SIDETONE assignment) and McBSPi.
[10] SIDETONEEN bit to 1.
NOTE:
Word width in the loop is 24 bits. If input channel word width is less than 24 bits, LSBs of
the samples are zero padded. If input channel word width is more than 24 bits, samples are
truncated.
describes the data exchange protocol between McBSP module and SIDETONE core:
3121
SWPU177N – December 2009 – Revised November 2010
Multi-Channel Buffered Serial Port
Copyright © 2009–2010, Texas Instruments Incorporated
