DSI protocol engine
DSI_PHY
DSI complex I/O
DSI_PHY
Clock
Serializer
Serializer
Lane 1
DDR clock
Lane 2
Registers - control logic
PPI
OCP
slave
CTRL
STALL
Video interface
(data [23:0], HS, VS, CLK,
PCLK, DE)
Interface
protocol
FIFO
Data
handler
Low
level protocol
–
Lane splitter
Data
handler
SINTERRUPT
DMA_Req[3:0]
dss-166
Public Version
www.ti.com
Display Subsystem Functional Description
Figure 7-87. DSI Protocol Engine
NOTE:
The order of the PHY pairs (clock and data lanes) is informative. Each PHY pair can be
Clock or Data. The DSI complex I/O receives the configuration for pin order and the
differ/- in a pair from the settings in DSS.
register.
The DSI serial interface is a bidirectional differential serial interface with data/clock for the physical layer
(configured in unidirectional link in case the display module is only unidirectional). The maximum DSI data
transfer capacity is 900 Mbps per channel. The speed of the link can be software configured only when
the DSI_PHY is in stop state or in ULPS.
shows the DSI transmitter/receiver high-level data flow.
1659
SWPU177N – December 2009 – Revised November 2010
Display Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated
