Texas Instruments OMAP36 Series, Technical Reference Manual

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Public Version
McBSP Register Manual
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Table 21-122. MCBSPLP_XCCR_REG
Address Offset 0x0000 00AC
Physical Address 0x4807 40AC Instance McBSP1
0x4809 60AC McBSP5
0x4902 20AC McBSP2
0x4902 40AC McBSP3
0x4902 60AC McBSP4
Description McBSPLP transmit configuration control register
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESERVED
DLB
XDMAEN
DXENDLY
XDISABLE
RESERVED RESERVED
PPCONNECT
EXTCLKGATE
XFULL_CYCLE
Bits Field Name Description Type Reset
31:16 RESERVED Read returns 0x0. R 0x0000
15 EXTCLKGATE External clock gating enable (CLKX and FSX master RW 0x0
only). When this bit is set and the transmit clock and FSX
are set as output, the CLKX is enabled when FSX is
active plus 3 clock cycles after (clock is provided for
FWID + 4 clock cycles, assuming that the FSX width,
active, is FWID + 1 clock cycles); outside this window the
external transmit clock is gated. The receive use the
same gated transmit clock and transmit frame
synchronization signals regardless of the CLKRM/FSRM
settings. When using this mode the frame
synchronization signal must be active during reception of
the entire frame (FWID must be programmed
accordingly) to ensure the proper receive process, which
requires at least 3 cycles after the frame complete to
transfer the data into the receive buffer.
0x0: External clock gating disabled.
0x1: External clock gating enable.
14 PPCONNECT Pair to pair connection. When set the DXENO pin is RW 0x0
always set to 0, regardless of the frame boundary, setting
the tree state buffer as output.
0x0: non Pair-to-pair connection. The DX pin will go to
high-impedance state when there is no frame to transmit.
0x1: Pair-to-pair connection. When set, the DXENO pin is
always set to 0, regardless of the frame boundary, setting
the tree state buffer as output. This means the DX pin will
be driven outside valid frame window. In that case, data
sent by McBSP module during inactive channel are not
guaranteed.
13:12 DXENDLY When McBSPi. MCBSPLP_SPCR1_REG [7] DXENA bit is RW 0x1
set to one, this field selects the added delay as follow:
0x0: 18 ns
0x1: 26 ns (default)
0x2: 35 ns
0x3: 42 ns
3198 Multi-Channel Buffered Serial Port SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated