Access engine
Address decoder
ECC
External memory port interface
FIFO
Prefetch and write-
posting engine
GPMC
configuration
L3 interconnect port interface
Address
NAND access only
Control
Data
Address
Chip-select
configuration
Address
CS selection
Data
gpmc-005
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General-Purpose Memory Controller
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Figure 10-5. GPMC Functional Diagram
The GPMC can access various external devices through the L3 Interconnect. The flexible programming
model allows a wide range of attached device types and access schemes.
Based on the programmed configuration bit fields stored in the GPMC registers, the GPMC is able to
generate all control signals timing depending on the attached device and access type.
Given the chip-select decoding and its associated configuration registers, the GPMC selects the
appropriate device type control signals timing.
10.1.4.2 L3 Interconnect Interface
The GPMC L3 interconnect interface is a pipelined interface including an 8 * 32-bit word write buffer.
Any system host can issue external access requests through the GPMC.
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Memory Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
