Texas Instruments OMAP36 Series, Technical Reference Manual

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Display Subsystem Register Manual
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Bits Field Name Description Type Reset
4:3 SIDLEMODE Slave interface power management, Idle req/ack control RW 0x2
0x0: Force-idle. An idle request is acknowledged unconditionally
0x1: No-idle. An idle request is never acknowledged
0x2: Smart-idle. Acknowledgement to an idle request is given based on
the internal activity of the module.
0x3: Reserved
2 ENWAKEUP Wake-up mode enable bit RW 0x0
0x0: Wakeup is disabled.
0x1: Wakeup is enabled,
1 SOFT_RESET Software reset. Set the bit to 1 to trigger a module reset. The bit is RW 0x0
automatically reset by the hw. During reads return 0.
0x0: Normal mode.
0x1: The module is reset
0 AUTO_IDLE Internal interface clock gating strategy RW 0x1
0x0: Interface clock is free-running.
0x1: Automatic Interface clock gating strategy is applied based on the
module interface activity.
Table 7-371. Register Call Summary for Register DSI_SYSCONFIG
Display Subsystem Integration
• Software Reset : [0]
• Clock Activity Mode : [1] [2] [3]
• Autoidle Mode : [4]
• Idle Mode : [5] [6] [7]
Display Subsystem Basic Programming Model
• Software Reset : [8]
• Power Management : [9] [10]
• Software Reset : [11]
Display Subsystem Use Cases and Tips
• Reset DSI Modules : [12]
• Reset DSI Modules : [13] [14] [15]
Display Subsystem Register Manual
• DSI Protocol Engine Register Mapping Summary : [16]
Table 7-372. DSI_SYSSTATUS
Address Offset 0x0000 0014
Physical Address 0x4804 FC14 Instance DSI_PROTOCOL_ENGINE
Description SYSTEM STATUS REGISTER This register provides status information about the module, excluding the
interrupt status register.
Type R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
RESET_DONE
1910 Display Subsystem SWPU177N – December 2009 – Revised November 2010
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