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Display Subsystem Integration
NOTE:
The display controller, the DSI protocol engine, and the RFBI modules also have their own
software reset functionality. To access this reset, access the DSS.
[1]
SOFTRESET bit for the display controller, the DSS.
[1] SOFTRESET bit for
the DSI protocol engine, and the DSS.
[1] SOFTRESET bit for the RFBI
module.
To properly reset these modules, 0x2 is the only valid value to write to these registers.
CAUTION
All the interface and functional clocks, even for the TV output, must be provided
to the display subsystem to update the RESETDONE status bit correctly.
7.3.1.3
Power Domain
The display subsystem modules are on the display subsystem (DSS) power domain and on the VDD2
voltage domain, except for the video DAC stage, which are on the analog vdda_dac voltage domain.
7.3.1.4
Power Management
7.3.1.4.1 Clock Activity Mode
The display controller clocks can be configured in one of the following clock activity modes:
•
DSS.
[9:8] CLOCKACTIVITY bit field set to 0x0 (reset value): The interface and
functional clocks can be switched off.
•
DSS.
[9:8] CLOCKACTIVITY bit field set to 0x1: The functional clocks can be can
be switched off and the interface clocks are maintained during the wake-up period.
•
DSS.
[9:8] CLOCKACTIVITY bit field set to 0x2: The interface clocks can be can
be switched off and the functional clocks are maintained during the wake-up period.
•
DSS.
[9:8] CLOCKACTIVITY bit field set to 0x3: The interface and functional
clocks are maintained during the wake-up period.
The DSI protocol engine clocks can be configured in one of the following clock activity modes:
•
DSS.
[9:8] CLOCKACTIVITY bit field set to 0x0 (reset value): The interface and
functional clocks can be switched off.
•
DSS.
[9:8] CLOCKACTIVITY bit field set to 0x1: The functional clocks can be
switched off and the interface clocks are maintained during the wake-up period.
•
DSS.
[9:8] CLOCKACTIVITY bit field set to 0x2: The interface clocks can be switched
off and the functional clocks are maintained during the wake-up period.
•
DSS.
[9:8] CLOCKACTIVITY bit field set to 0x3: The interface and functional
clocks are maintained during the wake-up period.
The DSS power domain clock activity status is logged in the PRCM.CM_CLKSTST_DSS[0]
CLKACTIVITY_DSS status bit. When set to 0, there is no domain clock activity. When set to 1, the DSS
power domain clock is active.
NOTE:
The display subsystem interface clock can be dependent on the DSS power domain state.
This is configured with PRCM.CM_AUTOIDLE_DSS[0] AUTO_DSS bit:
•
When the AUTO_DSS bit is set to 0 (reset value): The display subsystem interface clock
is not related to the DSS power domain state transition.
•
When the AUTO_DSS bit is set to 1: The display subsystem interface clock is
automatically enabled or disabled along with the DSS power domain state transition.
1623
SWPU177N – December 2009 – Revised November 2010
Display Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated
