Public Version
Display Subsystem Register Manual
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Table 7-246. RFBI_SYSCONFIG
Address Offset
0x10
Physical address
0x4805 0810
Instance
RFBI
Description
This register allows control of various parameters of the interconnect interface.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
AUTOIDLE
SIDLEMODE
SOFTRESET
Bits
Field Name
Description
Type
Reset
31:7
Reserved
Write 0s for future compatibility. Read returns 0.
RW
0x0000000
6
Reserved
Write 0s for future compatibility. Read returns 0.
RW
0
5
Reserved
Write 0s for future compatibility. Read returns 0.
RW
0
4:3
SIDLEMODE
Slave interface power management, Idle req/ack control
RW
0x0
00: Force-idle: Idle request is acknowledged unconditionally.
01: No idle: An idle request is never acknowledged
10: Smart idle: Idle request is acknowledged based on the internal
activity of the module.
11: Reserved
2
Reserved
Write 0s for future compatibility
RW
0
Read returns 0
1
SOFTRESET
Software reset
RW
0
Sets this bit to 1 to trigger a module reset. The bit is automatically
reset by the hardware. During reads, it always returns 0.
0: Normal mode
1: The module is reset
0
AUTOIDLE
Internal clock gating strategy (interconnectL4 and display controller
RW
1
clock)
0: Interconnect L4 clock and display controller clock are free-running.
1: Automatic clock gating strategy is applied for the interconnect L4
clock and display controller clock, based on the interconnect interface
and internal activity.
Table 7-247. Register Call Summary for Register RFBI_SYSCONFIG
Display Subsystem Integration
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1868
Display Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
