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Camera ISP Basic Programming Model
ADDR0=(2,0)
ADDR1=(855,2)
ADDR2=(1,1)
ADDR3=(856,1)
ADDR4=(0,2)
ADDR5=(857,0)
While not end_of_line
{
Write incoming pixel to ADDR0
ADDR0 += (1, 0)
Write incoming pixel to ADDR1
ADDR1 -= (1, 0)
Write incoming pixel to ADDR2
ADDR2 += (1, 0)
Write incoming pixel to ADDR3
ADDR3 -= (1, 0)
Write incoming pixel to ADDR4
ADDR4 += (1, 0)
Write incoming pixel to ADDR5
ADDR5 -= (1, 0)
}
Video Port
The 10-bit video-port output is enabled with
[15] VPEN = 1. Because the input data can
be up to 12 bits, one must select which 10 bits are selected with
[14:12] VPIN.
The output of the video port goes to the Preview module. At the output of the video port, the data rate is
resynchronized; the
[21:16] VPIF_FRQ bit field selects the video-output data rate as: L3
[21:16]VP 2) (from L3 speed/ 2 MHz to L3 speed/8 MHz). If
[21:16] VPIF_FRQ frequency is set too low compared to the input pixel clock, overflow
can occur.
6.5.6.6.2.6 Camera ISP CCDC Output Formatter
6.5.6.6.2.6.1 Camera ISP CCDC Low-Pass Filter
The low-pass filter is enabled with the
[14] LPF bit. When enabled, two pixels each in
the left and right edges of each line are cropped from the output.
6.5.6.6.2.6.2 Camera ISP CCDC A-Law Compression
A-Law compression is enabled by setting
[3] CCDTBL to 1. The A-Law table is fixed, so no
setup is required. When the input is wider than 10 bits, the
[2:0] GWDI bit is used to select
which 10 bits of the 12 possible bits are selected for compression. See
.
Table 6-66. Camera ISP CCDC CCDC_ALAW [2:0] GWDI
GWDI
Description
4
Bits 11 to 2
5
Bits 10 to 1
6
Bits 9 to 0
Others
Reserved
6.5.6.6.2.6.3 Camera ISP CCDC Culling
Culling performs a horizontal and vertical decimation function. The horizontal and vertical culling patterns
are set by the
register.
•
The 8-bit
[31:24] CULHEVN and
[23:16] CULHODD bit fields set
the horizontal culling pattern for even and odd lines. A 1 means that the pixel is retained; a 0 means
that the pixel is skipped. The same number of retained pixels must be set for even and odd lines.
•
The 8-bit
[7:0] CULV bit field sets the vertical culling pattern. The LSB represents the
top line and the MSB represents the bottom line. A 1 means that the line is retained; a 0 means that
the line is skipped.
1277
SWPU177N – December 2009 – Revised November 2010
Camera Image Signal Processor
Copyright © 2009–2010, Texas Instruments Incorporated
