Texas Instruments OMAP36 Series, Technical Reference Manual

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IVA2.2 Subsystem Register Manual
5.5.1.1 IC Register Mapping Summary
Table 5-23. IC Register Summary
Register Name Type Register Address Offset Physical Address
Width (Bits)
EVTFLAGi
(1)
R 32 0x0000 0000 0x0180 0000 + (0x4 * i)
EVTSETi
(1)
W 32 0x0000 0020 0x0180 0020 + (0x4 * i)
EVTCLRi
(1)
W 32 0x0000 0040 0x0180 0040 + (0x4 * i)
EVTMASKi
(1)
RW 32 0x0000 0080 0x0180 0080 + (0x4 * i)
MEVTFLAGi
(1)
R 32 0x0000 00A0 0x0180 00A0 + (0x4 * i)
EXPMASKi
(1)
RW 32 0x0000 00C0 0x0180 00C0 + (0x4 * i)
MEXPFLAGi
(1)
R 32 0x0000 00E0 0x0180 00E0 + (0x4 * i)
INTMUXj
(2)
RW 32 0x0000 0104 0x0180 0104 + (0x4 * j)
INTXSTAT R 32 0x0000 0180 0x0180 0180
INTXCLR W 32 0x0000 0184 0x0180 0184
INTDMASK RW 32 0x0000 0188 0x0180 0188
EVTASRT W 32 0x0000 01C0 0x0180 01C0
(1)
i = 0 to 3
(2)
j = 1 to 3
5.5.1.2 IC Register Descriptions
Table 5-24. EVTFLAGi
Address Offset (0x4*i)
Physical address 0x0180 0000 + (0x4*i) Instance IVA2.2 GEMIC
Description Event Flag Register
Type R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EF
Bits Field Name Description Type Reset
31:0 EF Event Flag status R 0
0: No event occurred
1: An event occurred
Table 5-25. Register Call Summary for Register EVTFLAGi
IVA2.2 Subsystem Functional Description
• INTC : [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10]
IVA2.2 Subsystem Basic Programming Model
• Event Combined Programming Sequence : [11]
• Interrupt Controller Basic Programming Model for Power On of IVA2.2 Subsystem : [12] [13] [14]
IVA2.2 Subsystem Register Manual
• IC Register Mapping Summary : [15]
805 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated