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IVA2.2 Subsystem Basic Programming Model
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Programming model for a correct warm-reset:
The software user must replay the noncombined events required for wakeup (if any):
1. Globally mask interrupts by setting the DSP CPU TSR[0] or CSR[0] GIE bit to 0 (already done at boot
time).
2. Restore the interrupt selector configuration:
(a) IVA_IC.
register (where j = {1 to 3})
(b) IVA_IC.
register (optional, where i = {0 to 3})
(c) IVA_IC.
register (optional)
3. Replay the noncombined event captured in IVA_IC.
(where i = {0 to 3}):
For each DSP CPU interrupt I = (4 to 15)
{
(a) Grab mapped event by setting the IVA_IC.
INTSELi[6:0] field (where j = {1 to 3}).
(b) Check if the event is combined (EVT0...3) or not combined (EVT4...127).
(c) If combined, exit the loop and go to next loop iteration.
(d) If noncombined:
(i) Check whether the event is pending in the IVA_IC.
EFy bit (where i = {0 to 3} and y
= {0 to 127}).
(ii) If not pending, exit the loop and go to the next loop iteration.
(iii) If pending, set the associated IFi bit in the DSP CPU IFR register.
}
NOTE:
Software must ensure that an event is enabled only once in the DSP megamodule interrupt
selector/combiner: If a noncombined event is mapped to an enabled DSP CPU interrupt, the
associated combined event is masked in the associated IVA_IC.
(where i = {0 to
3}) register (and/or the combined event is not mapped to the DSP CPU interrupt).
Reciprocally, if a combined event is mapped to a DSP CPU interrupt, all the unmasked
events in the associated IVA_IC.
(with i = {0, 1 to 3}) register are not mapped as
noncombined events to an enabled DSP CPU interrupt (through the DSP CPU IER register).
Software program example for Step 3:
/* ---------------------------------------------------- */
/* Replays IFR bits associated to noncombined events */
/* Assumes interrupts globally disabled (GIE bit set to 0)*/
/* Assumes IVA_IC.INTMUXj() and IVA_IC.EVTFLAGi() are access macros to DSP megamodule IC
registers */
/* ---------------------------------------------------- */
myIPR = IPR; // save IPR
for(I=0; i<12; I++) { // for each CPU maskable interrupt
myEvt = ( INTMUX( I >> 2 + 1) >> ( (I & 0x3) << 3 ) ) & 0x7F;
if(myEvt >= 4) { // noncombined event
if( (EVTFLAG(myEvt >> 5 ) >> (myEvt & 0x1F ) ) & 0x1 ) {
myIPR |= (1<<(I+4));
}
}
}
IPR=myIPR; // update IPR register
/* ---------------------------------------------------- */
/* Interrupts can be globally re-enabled from that point*/
/* ---------------------------------------------------- */
4. Restore the CPU interrupt configuration by setting the DSP CPU IER register accordingly.
5. Restore the IVA2.2 context (except saved return-PC).
6. Globally enable the interrupts by setting the DSP CPU TSR[0] or CSR[0] GIE bit to 1.
785
SWPU177N – December 2009 – Revised November 2010
IVA2.2 Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated