Texas Instruments OMAP36 Series, Technical Reference Manual

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IVA2.2 Subsystem Register Manual
Table 5-30. EVTMASKi
Address Offset (0x4*i)
Physical address 0x0180 0080 + (0x4*i) Instance IVA2.2 GEMIC
Description Event Mask Register
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EM
Bits Field Name Description Type Reset
31:0 EM Disables event from being used as input to the event combiner: RW 0
0: Will be combined
1: Is disabled from being combined.
Table 5-31. Register Call Summary for Register EVTMASKi
IVA2.2 Subsystem Functional Description
• INTC : [0] [1] [2] [3] [4] [5] [6] [7] [8]
IVA2.2 Subsystem Basic Programming Model
• Event Combined Programming Sequence : [9]
• Interrupt Controller Basic Programming Model for Power Down of IVA2.2 Subsystem : [10]
• Interrupt Controller Basic Programming Model for Power On of IVA2.2 Subsystem : [11] [12] [13] [14] [15]
IVA2.2 Subsystem Register Manual
• IC Register Mapping Summary : [16]
Table 5-32. MEVTFLAGi
Address Offset (0x4*i)
Physical address 0x0180 00A0 + (0x4*i) Instance IVA2.2 GEMIC
Description Masked Event Flag Register
Type R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEF
Bits Field Name Description Type Reset
31:0 MEF Masked Event Flag R 0
0: No unmasked event occurred
1: An unmasked event occurred
Table 5-33. Register Call Summary for Register MEVTFLAGi
IVA2.2 Subsystem Basic Programming Model
• Event Combined Programming Sequence : [0] [1] [2] [3]
IVA2.2 Subsystem Register Manual
• IC Register Mapping Summary : [4]
807 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem
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