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IVA2.2 Subsystem Basic Programming Model
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7. Branch to saved return-PC.
For a complete description of the DSP CPU TSR, CSR, IER, or IFR registers, see the C64x+
documentation (
).
•
Procedure for a correct cold reset
1. Globally mask interrupts by setting the DSP CPU TSR[0] or CSR[0] GIE bit to 0 (already done at boot
time).
2. Restore the interrupt selector configuration:
(a) IVA_IC.
register (where j = {1 to 3})
(b) IVA_IC.
register (optional, with i = {0 to 3})
(c) IVA_IC.
register (optional)
3. It is unnecessary to replay events, because they are masked in
and
registers (default WUGEN module configuration). This can be done to simplify the
boot sequence without discriminating between cold and warm reset.
4. Restore the CPU interrupt configuration by setting the DSP CPU IER REGISTER accordingly.
5. Restore the WUGEN module context. This can be forced even in warm reset to simplify the boot
sequence without discriminating between cold and warm reset.
NOTE:
If Steps 3 and 5 are performed systematically, the boot code can be shared between warm
and cold reset boot without programming two distinct software boot codes.
6. Restore the rest of the IVA2.2 subsystem context (except saved return-PC).
7. Globally enable the interrupts by setting the DSP CPU TSR[0] or CSR[0] GIE bit to 1.
8. Branch to saved return-PC.
5.4.8.7
Video and Sequencer Module interrupt Handling
5.4.8.7.1 Sequencer Interrupt
The sequencer uses a single FIQ interrupt. This single interrupt is driven by all the video accelerator
interrupts, DSP EDMA interrupts, DSP megamodule soft interrupts, and error interrupts. Registers are
available to manage these interrupts in the sequencer.
Before servicing an interrupt, the sequencer ISR must:
1. Identify the source event(s) for the interrupt line assertion
2. For each source event:
(a) Clear the interrupt at the source (in the module interrupt clear register)
(b) Clear the interrupt at the second-level (sequencer) interrupt controller
(c) Service the interrupt event
5.4.8.7.2 DSP Megamodule Interrupt
A single interrupt line is used per processor to gather all events that might require an interrupt of the DSP
megacell. This interrupt line is shared by all the modules responsible for generating an interrupt request to
the associated processor (iME, iLF, iVLCD, DSP megacell initiator error, DMA initiator error, and
sequencer soft interrupt). In turn, each of these modules has a single interrupt request output that is
shared by all events internal to the module.
Before servicing an interrupt, the processor (DSP megacell) ISR must:
1. Identify the source event(s) for the interrupt line assertion
2. For each source event:
(a) Clear the interrupt at the source (in the module interrupt clear register)
(b) Clear the interrupt at the second-level interrupt controller
(c) Clear the interrupt at the DSP interrupt controller (if combined interrupt is used, see
Event Combined Programming Sequence, for details)
(d) Service the interrupt event
3. Acknowledge the interrupt to the processor
786
IVA2.2 Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
