Texas Instruments OMAP36 Series, Technical Reference Manual

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IVA2.2 Subsystem Functional Description
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5.3.1.5 EMC Overview
The EMC is the megamodule component that reads or writes program and data external memory and
configuration registers, as requested by the UMC.
The EMC supports the following features:
• IDMA
• 64-bit slave port for accesses from an external DMA engine and/or host to L1 or L2 memory
• 64-bit master port to serve accesses from the UMC to external memory or configuration registers
The EMC operates to up to 182.5 MHz in the context the of the IVA2.2. The EMC can operate at half or
one third the frequency of the DSP.
CAUTION
Clock configurations depend on core voltage, and maximum clock
frequencies might not apply to production.
5.3.1.6 Memory Protection Overview
The DSP megamodule memory protection architecture divides the memory map into pages. Each page
has an associated set of permissions.
Memory protection provides many benefits to a system:
• Protects operating system data structures from poorly behaving code
• Helps in debugging by providing information about illegal memory accesses
• Prevents unauthorized access to sensitive data
• Allows the OS to enforce clearly defined boundaries between supervisor and user mode accesses,
leading to greater system robustness
Memory protection is implemented for the PMC, DMC, UMC, and EMC, and also for the IDMA and EDMA
modules.
5.3.1.7 INTC
The DSP megamodule INTC detects, potentially combines, and routes up to 128 system events (internal
and external) to the DSP CPU interrupt lines.
Table 5-5 lists the global interrupt mappings of the IVA2.2
subsystem (internal and external interrupts).
The DSP CPU has 12 maskable interrupts and one exception input. The INTC includes an interrupt
selector, an exception combiner, and an event combiner. The interrupt selector allows the routing of any of
the 128 system events (or a combination of them) to the 12 maskable interrupts of the DSP CPU, and
software determines the priorities of those system events. To handle potential conflicts, the 12 CPU
interrupts have fixed priorities. The exception combiner allows the combination of any of the 128 system
events to the single exception input of the DSP CPU (see
Figure 5-9 ).
710 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010
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