Texas Instruments OMAP36 Series, Technical Reference Manual

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IVA2.2 Subsystem Register Manual
Bits Field Name Description Type Reset
31:16 RESERVED Write 0s for future compatibility RW 0x0000
Read returns 0
15:12 SCANMODE Sets the scan mode (VLC/VLD) RW 0x0
00 Linear scan
01 Zig-Zag scan
10 Alternate vertical scan
11 Alternate horizontal scan
11 RESERVED Write 0s for future compatibility RW 0x0
Read returns 0
10:8 QSEL Quantization matrix selector RW 0x0
1 of 8 banks
7 RESERVED Write 0s for future compatibility RW 0x0
Read returns 0
6:4 IQSEL Inverse quantization matrix selector RW 0x0
1 of 8 banks
3 RESERVED Write 0s for future compatibility RW 0x0
Read returns 0
2:0 DCSEL DC predictor selector RW 0x0
1 of 6 banks
Table 5-615. Register Call Summary for Register VLCD_QIQ_CONFIGj
IVA2.2 Subsystem Basic Programming Model
• Setting Up Registers for Q/IQ Operation : [0]
IVA2.2 Subsystem Register Manual
• iVLCD Register Mapping Summary : [1]
Table 5-616. VLCD_VLD_ERRCTL
Address Offset 0x0000 10EC
Physical Address 0x0008 10EC Instance iVLCD
Description This register control the VLCD error enables.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
VLDENABLE
EOBENABLE
UVLDENABLE
Bits Field Name Description Type Reset
31:3 RESERVED Write 0s for future compatibility RW 0x0000
Read returns 0
2 EOBENABLE EOB error control RW 0x1
0: Off
1: On
1 VLDENABLE VLD error control. When JPEG or MPEG1/2 mode, thisbit should be RW 0x0
set to 0 (off).
0: Off
1: On
0 UVLDENABLE UVLD error control RW 0x0
0: Off
1: On
1029 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem
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