Texas Instruments OMAP36 Series, Technical Reference Manual

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PRCM Register Manual
Bits Field Name Description Type Reset
31:29 RESERVED Write 0s for future compatibility. Reads returns 0. R 0x00
28 VC_BYPASS_ACK_ST Voltage controller's acknowledge to the bypass interface RW 0
status. It is cleared by software. dual
Read 0x0: Voltage controller's acknowledge to the
bypass interface event is false.
Write 0x0: Status bit unchanged.
Read 0x1: Voltage controller's acknowledge to the
bypass interface event is true (pending).
Write 0x1: Status bit is cleared to 0.
27 VC_VP1_ACK_ST Voltage controller's acknowledge to the VDD1 voltage RW 0
processor status. It is cleared by software. dual
Read 0x0: Voltage controller's acknowledge to the VDD1
voltage processor event is false.
Write 0x0: Status bit unchanged.
Read 0x1: Voltage controller's acknowledge to the VDD1
voltage processor event is true (pending).
Write 0x1: Status bit is cleared to 0.
26 ABB_LDO_TRANXDONE_ST ABB LDO transaction completion status. This status is RW 0
set when a software-initiated transaction is completed in dual
ABB LDO (active mode transition only). It is cleared by
software.
Read 0x0: ABB LDO transaction done event is false.
Write 0x0: Status bit unchanged.
Read 0x1: ABB LDO transaction done event is true
(pending).
Write 0x1: Status bit is cleared to 0.
25 SND_PERIPH_DPLL_ST DPLL5 recalibration event status RW 0x0
Read 0x0: DPLL5 recalibration event is false
Write 0x0: Status bit unchanged
Read 0x1: DPLL5 recalibration event is true (pending)
Write 0x1: Status bit is cleared to 0.
24 VC_TIMEOUTERR_ST Voltage Controller timeout error event status RW 0x0
Read 0x0: Voltage Controller timeout error event is false
Write 0x0: Status bit unchanged
Read 0x1: Voltage Controller timeout error event is true
(pending)
Write 0x1: Status bit is cleared to 0.
23 VC_RAERR_ST Voltage Controller register address acknowledge error RW 0x0
event status
Read 0x0: Voltage Controller register address
acknowledge error event is false
Write 0x0: Status bit unchanged
Read 0x1: Voltage Controller register address
acknowledge error event is true (pending)
Write 0x1: Status bit is cleared to 0.
22 VC_SAERR_ST Voltage Controller slave address acknowledge error RW 0x0
event status
Read 0x0: Voltage Controller slave address acknowledge
error event is false
Write 0x0: Status bit unchanged
Read 0x1: Voltage Controller slave address acknowledge
error event is true (pending)
Write 0x1: Status bit is cleared to 0.
561 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management
Copyright © 2009–2010, Texas Instruments Incorporated