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SDRAM Controller (SDRC) Subsystem
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The start address for CS1 is defined by the SDRC.
[9:8] CS1STARTLOW and
SDRC.
[3:0] CS1STARTHIGH fields.
Space 0, selected by the SDRC using the CS0 (nCS0) output pin, is always at offset 0 from the SDRAM
memory space base address. The size of this area is programmable through the
SDRC.
[17:8] RAMSIZE field, where p = 0. Space 1, selected by the SDRC using the CS1
(nCS1) output pin, is at an offset from the SDRAM memory space base address; this offset is
programmable in 128M-byte increments. The size of this area is programmable through the
SDRC.
[17:8] RAMSIZE field, where p = 1. The type of device for each area is
programmable through the SDRC.
register (where p = 0 or 1 for SDRC CS0 or CS1).
NOTE:
Ensure that space 0 and space 1 do not overlap each other or extend farther than the
maximum 1G-byte SDRC memory space, as explained in
, Global Memory Space
Mapping, of
, Memory Mapping.
10.2.5.3.2 Memory Configuration
The memory configuration is defined on a per-CS basis through the SDRC.
register
(where p = 0 or 1 for SDRC CS0 or CS1).
lists the memory configuration.
Table 10-104. Memory Configuration
Bit Field
Comments
ADDRMUXLEGACY
Address multiplexing scheme
RAMSIZE
Defines the physical RAM address space in terms of 2M -byte chunks
B32NOT16
External device data bus width.
DEEPPD
Set this bit if the memory supports deep-power-down mode. (This bit is only a flag for software. It
does not affect any SDRC function.)
DDRTYPE
Mobile DDR
RAMTYPE
Single Data Rate or Double Data Rate SDRAM
NOTE:
Exported Register Reset Values and Lock Bit
The reset values of SDRC.
and SDRC.
are exported in the
control module. At reset, these registers take the value previously stored in the control
module. A new bit is added to each register to provide the capability to lock these three
registers into read-only accesses:
•
SDRC.
[30] LOCKSTATUS bit (p = 0 or 1 for CS0 or CS1)
•
SDRC.
[30] LOCK bit
The reset value of each lock bit is also imported from the control module.
10.2.5.3.3 SDRAM AC Timing Parameters
The AC parameters described in
can be independently programmed (standard JEDEC
LPDDR1 terminology is used here) in clock cycles for each of the two memory areas through registers
SDRC.
and SDRC.
(p = 0 or 1, depending on the CS
area).
Table 10-105. Programmable AC Parameters
SDRC
Description
Range
AC Parameter
(Clock Ticks)
tRFC
AUTO REFRESH to ACTIVE / AUTO REFRESH command period (autoReFresh
0 - 31
Cycle time)
tRC
ACTIVE to ACTIVE command period (Row Cycle time)
0 - 31
tRAS
ACTIVE to PRECHARGE command period
0 - 15
2268Memory Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
