Public Version
Global Memory Space Mapping
www.ti.com
2.2
Global Memory Space Mapping
This section provides a global view of the memory mapping and describes the boot, GPMC, SDRC, and
virtual rotated frame buffer (VRFB) memory spaces.
The system memory mapping is flexible, with two levels of granularity for target address space allocation:
•
Level 1 (L1): Four quarters are labeled Q0, Q1, Q2, and Q3. Each quarter corresponds to a 1-GB
address space (total address space is 4GB).
•
Level 2 (L2): Each quarter is divided into eight blocks of 128MB, with target spaces mapped in the
blocks.
This organization allows all target spaces to be decoded based on the five most-significant bits (MSBs) of
the 32-bit address ([31:27]).
•
Boot space
The system has a 1-MB boot space in the on-chip boot ROM or on the GPMC memory space.
When booting from the on-chip ROM with the appropriate external sys_boot5 pin configuration, the
1-MB memory space is redirected to the on-chip boot ROM memory address space [0x4000 0000 –
0x400F FFFF].
When booting from the GPMC with the appropriate external sys_boot5 pin configuration, the memory
space is part of the GPMC memory space.
For more information about sys_boot5 pin configuration, see
, Memory Subsystem, and
, Initialization.
•
GPMC space
Eight independent GPMC chip-selects (gpmc_ncs0 to gpmc_ncs7) are available in the first quarter
(Q0) of the addressing space to access NOR/NAND flash and SRAM memories. The chip-selects have
a programmable start address and programmable size (16, 32, 64, or 128MB) in a total memory space
of 1GB.
•
SDRC space
Two SDRC chip-selects (sdrc_ncs0 and sdrc_ncs1) are available on the third quarter (Q2) of the
addressing space to access SDRAM memories. The chip-selects have a programmable size (64, 128,
or 256MB) in a total memory space of 1GB (256MB per chip-select).
The base address of the chip-select 0 (sdrc_ncs0) memory space is always 0x8000 0000. The base
address of the chip-select 1 (sdrc_ncs1) memory space is programmable. The default value after reset
is 0xA000 0000.
•
VRFB space
The SDRC-SMS virtual memory space is a different memory space used to access a subset of the
SDRC memory space through the rotation engine (ROT). The virtual address space size is 768MB split
into two parts: The first 256-MB part is in the second quarter (Q1) of the memory; the second 512-MB
part is in the fourth quarter (Q3) of the memory.
For more information about boot, GPMC, SDRC, and VRFB, see
, Memory Subsystem.
This section describes all modules and features in the high-tier device. In unavailable modules and
features, the memory area is reserved, read is undefined, and write can lead to unpredictable behavior.
describes the global memory space mapping.
206
Memory Mapping
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
