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SDMA Functional Description
NOTE:
If the channel intended to be used is a drain candidate, always enable DRAIN END
INTERRUPT for that channel.
When the sDMA is in smart standby mode, before disabling a drain candidate channel
(DMA4_CCRi[7] ENABLE = 0x0), the sDMA must be configured to be in force standby mode
(DMA4_OCP_SYSCONFIG[13:12] = 0x0) or in no standby mode
(DMA4_OCP_SYSCONFIG[13:12] = 0x1). After the occurrence of DRAIN END INTERRUPT
EVENT from that channel, the sDMA can be switched back to smart standby mode
(DMA4_OCP_SYSCONFIG[13:12] = 0x2).
11.4.19 Linked List
11.4.19.1 Overview
The SDMA supports the logical transfer descriptor loader feature. A transfer descriptor represents a set of
values that maps to a set of logical channel configuration registers.
A logical channel transfer descriptor can be loaded by DMA from memories, then successive transfer
descriptors can be autonomously loaded according to a linked-list scheme. This enables DMA4 scatter
gather transfers with minimum MPU support by removing successive channel configuration processing
and the associated interrupt handling overheads. It also optimizes DMA4 channel resources by enabling
efficient transfer serialization on a single logical channel versus concurrent (multiple) logical channel use.
Different types of transfer descriptors are supported (full or partial logical channel configuration registers
are set). This optimizes the memory size required for storing a long linked list, because parameter
changes are limited to only a few logical channel configuration registers.
11.4.19.2 Link-List Transfer Profile
A linked-list transfer can be seen as a super-block transfer (where the block is composed of FN frames
and each frame includes EN elements). In a super block. The block size (FN x EN x ES) can be changed
in the linked list by loading an updated transfer descriptor.
The end of the super block is signaled in the last descriptor associated with the last block. Generally, for a
given link-list transfer, the logical channel is set at the beginning of the transfer and the logical channel
configurations for the subsequent blocks are slightly changed. Thus, the descriptor can be limited to an
update of only few parameters, like FN or EN. This assumes that the content of unmodified registers is
preserved when a new descriptor is loaded.
A transfer descriptor is composed of a set of channel configuration register values with the addition of the
next-descriptor pointer register (
) and a channel-descriptor parameter register
(
) . The next-descriptor pointer is the 32-bit address pointer from where the next transfer
descriptor is to be loaded.
Using the next-descriptor pointer, the user can also stop a link-list transfer by setting the
DMA4_CNDPi[31:2] NEXT_DESCRIPTOR_POINTER bit field of the last descriptor to 0x3FFF FFFF (that
is, setting the DMA4_CNDPi[31:0] bit field to 0xFFFF FFFC).
CAUTION
The setting of the DMA4_CNDPi[31:2] NEXT_DESCRIPTOR_POINTER bit
field must be done only through the descriptor load (that is, only from the
descriptor content). This is because once the channel is configured and
enabled, it is not recommended to change the configuration through
configuration port access. However, if there are no descriptors in the link-list
chain, but still making the channel a descriptor (type 1, 2, 3) candidate, the user
can
configure
the
value
0x3FFF
FFFF
into
the
DMA4_CNDPi[31:2]
NEXT_DESCRIPTOR_POINTER
bit
field
(0xFFFF
FFFC
into
DMA4_CNDPi[31:0]) through configuration port access.
2361
SWPU177N – December 2009 – Revised November 2010
SDMA
Copyright © 2009–2010, Texas Instruments Incorporated
