Public Version
Camera ISP Register Manual
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Bits
Field Name
Description
Type
Reset
3
IRQ_CBUFF1_READY
The CPUW1 physical buffer is ready to be accessed by
R/W/1to
0x0
the CPU.
Clr
0x0: No done interrupt pending (r); Status unchanged
(w).
0x1: Done interrupt pending (r); Status bit cleared (w).
2
IRQ_CBUFF0_OVR
Buffer overflow event.
R/W/1to
0x0
Clr
0x0: No done interrupt pending (r); Status unchanged
(w).
0x1: Done interrupt pending (r); Status bit cleared (w).
1
IRQ_CBUFF0_INVALID
Invalid access.
R/W/1to
0x0
Clr
0x0: No YUV buffer done interrupt pending (r); Status
unchanged (w).
0x1: YUV buffer done interrupt pending (r); Status bit
cleared (w).
0
IRQ_CBUFF0_READY
The CPUW0 physical buffer is ready to be accessed by
R/W/1to
0x0
the CPU.
Clr
0x0: No done interrupt pending (r); Status unchanged
(w).
0x1: Done interrupt pending (r); Status bit cleared (w).
Table 6-126. Register Call Summary for Register CBUFF_IRQSTATUS
Camera ISP Integration
•
Camera ISP Functional Description
•
Camera ISP Circular Buffer Window Management
Camera ISP Basic Programming Model
•
:
•
Camera ISP CBUFF Status Checking
Camera ISP Register Manual
•
Camera ISP CBUFF Register Summary
Table 6-127. CBUFF_IRQENABLE
Address Offset
0x0000 001C
Physical Address
0x480B C11C
Instance
ISP_CBUFF
Description
The interrupt enable register allows to enable/disable the module internal sources of interrupt, on an
event-by-event basis.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
IRQ_CBUFF1_OVR
IRQ_CBUFF0_OVR
IRQ_CBUFF1_READY
IRQ_CBUFF0_READY
IRQ_CBUFF1_INVALID
IRQ_CBUFF0_INVALID
Bits
Field Name
Description
Type
Reset
31:6
RESERVED
Write 0s for future compatibility. Reads return zero.
RW
0x0000000
5
IRQ_CBUFF1_OVR
Buffer overflow event.
RW
0x0
0x0: interrupt is masked
0x1: Interrupt is enabled
1332
Camera Image Signal Processor
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated