Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 1148 / 3738

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Camera ISP Integration
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Table 6-16. Camera ISP CBUFF Interrupt Details (continued)
Event Mask Description
CBUFF_IRQSTATUS [3] CBUFF_IRQENABLE [3] The CPUW1 physical buffer is ready to be
IRQ_CBUFF1_READY IRQ_CBUFF1_READY accessed by the CPU.
CBUFF_IRQSTATUS [2] CBUFF_IRQENABLE [2] IRQ_CBUFF0_OVR Buffer overflow event. See description of
IRQ_CBUFF0_OVR IRQ_CBUFF1_OVR event.
CBUFF_IRQSTATUS [1] CBUFF_IRQENABLE [1] Invalid access. See description of
IRQ_CBUFF0_INVALID IRQ_CBUFF0_INVALID IRQ_CBUFF1_INVALID event.
CBUFF_IRQSTATUS [0] CBUFF_IRQENABLE [0] The CPUW1 physical buffer is ready to be
IRQ_CBUFF0_READY IRQ_CBUFF0_READY accessed by the CPU
Table 6-17 describes the CSI1/CCP2B receiver interrupts.
Table 6-17. Camera ISP CSI1/CCP2B Receiver Interrupt Details
Event Mask Description
CCP2_LC01_IRQSTATUS [27] CCP2_LC01_IRQENABLE [27] LC1_FS_IRQ Frame-start synchronization code detection for
LC1_FS_IRQ logical channel 1:
This interrupt is triggered on the detection of a
frame-start synchronization code into the CCP2
data stream.
CCP2_LC01_IRQSTATUS [26] CCP2_LC01_IRQENABLE [26] LC1_LE_IRQ Line-end synchronization code detection for
LC1_LE_IRQ logical channel 1:
This interrupt is triggered on the detection of a
line-end synchronization code into the CCP2 data
stream.
CCP2_LC01_IRQSTATUS [25] CCP2_LC01_IRQENABLE [25] LC1_LS_IRQ Line-start synchronization code detection for
LC1_LS_IRQ logical channel 1:
This interrupt is triggered on the detection of a
line-start synchronization code into the CCP2 data
stream.
CCP2_LC01_IRQSTATUS [24] CCP2_LC01_IRQENABLE [24] LC1_FE_IRQ Frame-end synchronization code detection for
LC1_FE_IRQ logical channel 1:
This interrupt is triggered on the detection of a
frame-end synchronization code into the CCP2
data stream.
CCP2_LC01_IRQSTATUS [23] CCP2_LC01_IRQENABLE [23] Frame counter reached for logical channel 1:
LC1_COUNT_IRQ LC1_COUNT_IRQ This interrupt is triggered when the frame counter
has reached its programmable target value.
CCP2_LC01_IRQSTATUS [21] CCP2_LC01_IRQENABLE [21] FIFO overflow error for logical channel 1:
LC1_FIFO_OVF_IRQ LC1_FIFO_OVF_IRQ This interrupt is triggered upon detection of a
FIFO overflow. An overflow can occur if there is a
mismatch between the data input and output
rates.
CCP2_LC01_IRQSTATUS [20] CCP2_LC01_IRQENABLE [20] CRC error for logical channel 1:
LC1_CRC_IRQ LC1_CRC_IRQ This interrupt is triggered upon detection of a
mismatch between the transmitter and receiver
checksums. This interrupt does not apply to the
MIPI CSI1 compatible mode.
CCP2_LC01_IRQSTATUS [19] CCP2_LC01_IRQENABLE [19] False synchronization code protection error for
LC1_FSP_IRQ LC1_FSP_IRQ logical channel 1:
This interrupt is triggered by the FSP decoder if an
illegal combination is detected, but 0xA5 is not
present in the bit stream.
CCP2_LC01_IRQSTATUS [18] CCP2_LC01_IRQENABLE [18] LC1_FW_IRQ Frame-width error for logical channel 1:
LC1_FW_IRQ This interrupt is generated if the frame width
constraints associated to the current data type is
not respected.
CCP2_LC01_IRQSTATUS [17] CCP2_LC01_IRQENABLE [17] False synchronization code error for logical
LC1_FSC_IRQ LC1_FSC_IRQ channel 1:
This interrupt is triggered if the synchronization
code order is not respected. This state is shown in
the CCP2 receiver finite state-machine.
1148 Camera Image Signal Processor SWPU177N – December 2009 – Revised November 2010
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