Texas Instruments OMAP36 Series, Technical Reference Manual

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Camera ISP Integration
Table 6-15. Camera ISP Interrupts (continued)
Event Mask Description
ISP_IRQ0STATUS [6] CSI1_LC2_IRQ ISP_IRQ0ENABLE [4] CSI1_LC2_IRQ CSI1/CCP2B receiver module event. See
CCP2_LC23_IRQSTATUS to know which interrupt
it is.
ISP_IRQ0STATUS [5] CSI1_LC1_IRQ ISP_IRQ0ENABLE [4] CSI1_LC1_IRQ CSI1/CCP2B receiver module event. See
CCP2_LC01_IRQSTATUS to know which interrupt
it is.
ISP_IRQ0STATUS [4] CSI1_LC0_IRQ ISP_IRQ0ENABLE [4] CSI1_LC0_IRQ CSI1/CCP2B receiver module event. See
CCP2_LC01_IRQSTATUS to know which interrupt
it is.
ISP_IRQ0STATUS [3] ISP_IRQ0ENABLE [3] CSI1_LCM_IRQ CSI1 receiver module event on memory channel.
CSI1_LCM_IRQ
ISP_IRQ0STATUS [1] CSI2C_IRQ ISP_IRQ0ENABLE [1] CSI2C_IRQ CSI2C receiver module event. See
CSI2_IRQSTATUS to know which interrupt it is.
ISP_IRQ0STATUS [0] CSI2A_IRQ ISP_IRQ0ENABLE [0] CSI2A_IRQ CSI2A receiver module event. See
CSI2_IRQSTATUS to know which interrupt it is.
NOTE: n is equal to 0 or 1.
I is equal to 01 or 23.
Table 6-16 summarizes the CBUFF interrupts.
Table 6-16. Camera ISP CBUFF Interrupt Details
Event Mask Description
CBUFF_IRQSTATUS [5] CBUFF_IRQENABLE [5] IRQ_CBUFF1_OVR Buffer overflow event: The generation of this event
IRQ_CBUFF1_OVR depends on the
CBUFFx_CTRL .ALLOW_NW_EQ_CR flag and
the circular buffer mode (read or write). This event
indicates a bandwidth mismatch between data
producer and data consumer. When it occurs,
CBUFFx does NOT go into error state. However,
the data in the physical buffer is very likely to be
corrupted.
CBUFF_IRQSTATUS [4] CBUFF_IRQENABLE [4] Invalid access:
IRQ_CBUFF1_INVALID IRQ_CBUFF1_INVALID
• Camera controller writes the virtual space of
CBUFFx in read mode.
• Camera controller reads the virtual space of
CBUFFx in write mode.
• HW writes the virtual space of circular buffer
x outside the CW or NW window in write
mode.
• HW reads the virtual space of circular buffer
x outside the CW or NW window in read
mode.
• NW full
• CPU write the DONE bit when physical
buffers are not ready for the CPU.
This event indicates a wrong configuration of the
circular buffer, the camera ISP, or bogus software.
When it occurs, CBUFFx goes into an error state.
In this state all accesses to the virtual space of
CBUFFx are cancelled: they are not forwarded to
the physical space. The purpose is to prevent
corruption of the physical memory.
The error state can be left by disabling the
CBUFFx and reenabling it. Before doing so, the
SW must ensure that there are no more
outstanding requests to the virtual space of
CBUFFx.
1147 SWPU177N – December 2009 – Revised November 2010 Camera Image Signal Processor
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