Texas Instruments OMAP36 Series, Technical Reference Manual

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Camera ISP Register Manual
Table 6-645. CSI2_IRQSTATUS
Address Offset 0x0000 0018
Physical Address Instance See Table 6-80
See Table 6-638
Description INTERRUPT STATUS REGISTER - All contexts
This register associates one bit for each context in order to determine which context has generated the
interrupt. The context shall be enabled for events to be generated on that context.
If the context is disabled, the interrupt is not generated.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
CONTEXT7 CONTEXT6 CONTEXT5 CONTEXT4 CONTEXT3 CONTEXT2 CONTEXT1 CONTEXT0
RESERVED
OCP_ERR_IRQ FIFO_OVF_IRQ
SHORT_PACKET_IRQ
COMPLEXIO1_ERR_IRQ
ECC_CORRECTION_IRQ
ECC_NO_CORRECTION_IRQ
Bits Field Name Description Type Reset
31:15 RESERVED Write 0s for future compatibility. Read returns 0. R 0x00000
14 OCP_ERR_IRQ Interconnect Error Interrupt RW 0
W1toClr
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
13 SHORT_PACKET_IRQ Short packet reception status (other than synch events: RW 0
Line Start, Line End, Frame Start, and Frame End: data W1toClr
type between 0x8 and x0F only shall be considered).
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
12 ECC_CORRECTION_IRQ ECC has been used to do the correction of the only 1-bit RW 0
error status (short packet only). W1toClr
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
11 ECC_NO_CORRECTION_IRQ ECC error status (short and long packets). No correction RW 0
of the header because of more than 1-bit error. W1toClr
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
10 RESERVED Write 0s for future compatibility. Read returns 0. R 0x00000
9 COMPLEXIO1_ERR_IRQ Error signaling from Complex I/O #1: status of the PHY R 0
errors received from Complex I/O #1 (events are defined
in
CSI2_COMPLEXIO1_IRQSTATUS for the first
complex I/O).
Read 0x0: READS: Event is false.
Read 0x1: READS: Event is true (pending).
1525 SWPU177N – December 2009 – Revised November 2010 Camera Image Signal Processor
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