Texas Instruments OMAP36 Series, Technical Reference Manual

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Camera ISP Register Manual
Bits Field Name Description Type Reset
2:0 CLOCK_POSITION Position and order of the CLOCK lane. The clock lane is RW 0x0
always present.
0x0: Not used/connected
0x1: Clock lane is at position 1.
0x2: Clock lane is at position 2.
0x3: Clock lane is at position 3.
0x5: Clock lane is at position 2 (using CSIPHY1) or 1
(using CSIPHY2). This setting is valid for CCP2 receiver
mode only.
Note: The settings differ when using CSIPHY1/CSIPHY2
and CCP2. See
Section 6.5.2.2 , Camera ISP CSIPHY
Initialization for Work With CSI1/CCP2B Receiver.
Table 6-656. Register Call Summary for Register CSI2_COMPLEXIO_CFG1
Camera ISP Environment
• Camera ISP Connectivity Schemes : [0]
Camera ISP Functional Description
• Camera ISP CSI2 Physical Layer Lane Configuration : [1] [2] [3]
• Camera ISP CSI2 PHYs : [4] [5] [6]
Camera ISP Basic Programming Model
• Camera ISP CSIPHY Initialization for Work With CSI2 Receiver : [7] [8] [9] [10] [11] [12]
• Camera ISP CSIPHY Initialization for Work With CSI1/CCP2B Receiver : [13] [14] [15] [16] [17] [18]
Camera ISP Register Manual
• Camera ISP CSI2 REGS1 Register Summary : [19]
Table 6-657. CSI2_COMPLEXIO1_IRQSTATUS
Address Offset 0x0000 0054
Physical Address Instance See Table 6-80
See Table 6-638
Description INTERRUPT STATUS REGISTER - All errors from the associated PHY
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
ERRESC5 ERRESC4 ERRESC3 ERRESC2 ERRESC1
ERRSOTHS5 ERRSOTHS4 ERRSOTHS3 ERRSOTHS2 ERRSOTHS1
STATEULPM5 STATEULPM4 STATEULPM3 STATEULPM2 STATEULPM1
ERRCONTROL5 ERRCONTROL4 ERRCONTROL3 ERRCONTROL2 ERRCONTROL1
ERRSOTSYNCHS5 ERRSOTSYNCHS4 ERRSOTSYNCHS3 ERRSOTSYNCHS2 ERRSOTSYNCHS1
STATEALLULPMEXIT
STATEALLULPMENTER
Bits Field Name Description Type Reset
31:27 RESERVED Write 0s for future compatibility. Read returns 0. R 0x00
26 STATEALLULPMEXIT At least one of the active lanes has exit the ULPM RW 0
W1toClr
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
25 STATEALLULPMENTER All active lanes are entering in ULPM. RW 0
W1toClr
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
1533 SWPU177N – December 2009 – Revised November 2010 Camera Image Signal Processor
Copyright © 2009–2010, Texas Instruments Incorporated