Texas Instruments OMAP36 Series, Technical Reference Manual

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Camera ISP Register Manual
Bits Field Name Description Type Reset
31:30 RESERVED Write 0s for future compatibility. Read returns 0. RW 0x0
29:20 PRV_EXP PREVIEW module READ request expand RW 0x000
Sets the number of clock cycles (func clock cycles) to
allow btw two consecutive READ requests from the
module.
It spreads non-real time read requests over time.
It enables less priority in the system not to be locked out.
At maximum, the PRV and CCP2_RD can read 256 bytes
every 32*PRV_EXP functional clock cycles.
19:10 RSZ_EXP RESIZER module READ request expand RW 0x000
Sets the number of clock cycles (func clock cycles) to
allow btw two consecutive READ requests from the
module.
It spreads non-real time read requests over time.
It enables less priority in the system not to be locked out.
At maximum, the RSZ can read 256 bytes every
32*RSZ_EXP functional clock cycles.
9:0 HIST_EXP HISTOGRAM module READ request expand RW 0x000
Sets the number of clock cycles to allow btw two
consecutive READ requests from the module.
It spreads non-real time read requests over time.
It enables less priority in the system not to be locked out.
At maximum, the HIST can read 256 bytes every
HIST_EXP functional clock cycles.
Table 6-637. Register Call Summary for Register SBL_SDR_REQ_EXP
Camera ISP Basic Programming Model
• Camera ISP Resizer Events and Status Checking : [0]
• Camera ISP Central-Resource SBLRegister Setup : [1]
• Camera ISP Central-Resource SBL Input From Memory : [2] [3] [4] [5]
Camera ISP Register Manual
• Camera ISP SBL Register Summary : [6]
6.6.10 Camera ISP CSI2 Registers
6.6.10.1 Camera ISP CSI2 REGS1 Register Summary
Table 6-638. CAMERA_ISP_CSI2_REGS1 Register Summary
Register CAMERA_ISP_CSI CAMERA_ISP_CSI
Register Name Type Width Address Offset 2A_REGS1 L3 2C_REGS1 L3
(Bits) Base Address Base Address
CSI2_REVISION R 32 0x0000 0000 0x480B D800 0x480B DC00
CSI2_SYSCONFIG RW 32 0x0000 0010 0x480B D810 0x480B DC10
CSI2_SYSSTATUS R 32 0x0000 0014 0x480B D814 0x480B DC14
CSI2_IRQSTATUS RW 32 0x0000 0018 0x480B D818 0x480B DC18
CSI2_IRQENABLE RW 32 0x0000 001C 0x480B D81C 0x480B DC1C
CSI2_CTRL RW 32 0x0000 0040 0x480B D840 0x480B DC40
CSI2_DBG_H W 32 0x0000 0044 0x480B D844 0x480B DC44
CSI2_GNQ R 32 0x0000 0048 0x480B D848 0x480B DC48
RESERVED RW 32 0x0000 004C 0x480B D84C 0x480B DC4C
CSI2_COMPLEXIO_CFG1 RW 32 0x0000 0050 0x480B D850 0x480B DC50
CSI2_COMPLEXIO1_IRQSTAT
RW 32 0x0000 0054 0x480B D854 0x480B DC54
US
RESERVED RW 32 0x0000 0058 0x480B D858 0x480B DC58
CSI2_SHORT_PACKET R 32 0x0000 005C 0x480B D85C 0x480B DC5C
CSI2_COMPLEXIO1_IRQENAB
RW 32 0x0000 0060 0x480B D860 0x480B DC60
LE
1521 SWPU177N – December 2009 – Revised November 2010 Camera Image Signal Processor
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