camisp-092
Pixels
Frame read from memory –
processed very fast though it is not
always required and other
requestors are potentially blocked
for significant amounts of time
Lines
Expand processing time per
frame – still okay because
total throughput is the same
(just distributed)
Public Version
Camera ISP Basic Programming Model
www.ti.com
6.5.11.5.2 Camera ISP Central-Resource SBL Input From Memory
When the input image is from memory, data is fetched from memory and processed at a steady state rate
of 200 MB/sec. Depending on the image size and real-time deadline for each frame, this may be much
faster than necessary. Such activity can also starve other processes in the system. Internally, when a
CAMERA ISP module receives input from memory, the CAMERA ISP makes a read request to the L3
interconnect whenever there is available memory in its internal buffers.
The
register can be programmed to control the rate at which a camera ISP module
(Preview, resizer, or histogram) reads the input frame from memory. This indirectly controls the output
bandwidth of the preview engine and resizer. Depending on the size of the images and the real-time
deadlines, users can set this field appropriately and balance the bandwidth requirements to memory.
The minimum number of cycles (L3) in between read requests used to program the
register can be determined based on the frame size and real-time requirement using the following
equation:
Number of cycles/request = (DMA cycles/frame) / (DMA read requests/frame)
In the previous equation, (DMA cycles/frame) is based on a real-time requirement. For example, if the
real-time requirement is a frame rate of 1/30 sec and the L3 clock equals the ISP clock, this can be
calculated as:
(DMA cycles/frame) = L3 clock * frame rate = ISP clock * 1/30 = 5.53M cycles
The (DMA read requests/frame) is based on the frame size and the alignment in memory. Assuming a
VGA (640 x 480) frame size and optimal alignment conditions:
(DMA read requests/frame) = Transfers per line * number of lines = 640 pix/line*2 bytes/pix/256
bytes/xfer * 480 lines = 2400 requests/frame
In this example, the final equation can now be solved:
Number of cycles/request = 5.53M cyles/2400 requests = 2306 cycles/request
demonstrates how this register can expand processing time for lower real-time requirements.
Figure 6-121. Camera ISP Central-Resource SBL Memory Read Bandwidth Balancing
The maximum values that can be written to the
register for the different read
requesters is 1023. For the histogram and preview engine, this should be sufficient for the typical size of
RAW data frames. However, because the resizer can read a variety of video frame sizes, the field for the
resizer is internally multiplied by 32. Therefore, for this example, the
RSZ_EXP bit field can be programmed to FLOOR(2306/32) = 72.
The previous equations provide an estimate or a starting point for programming this register. Depending
on the system loads and available bandwidth, it may be necessary to reduce this number to compensate
for a heavily loaded system.
1298
Camera Image Signal Processor
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated