Texas Instruments OMAP36 Series, Technical Reference Manual

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Camera ISP Register Manual
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Table 6-90. ISP_IRQ0STATUS
Address Offset 0x0000 0010
Physical Address Instance ISP
See Table 6-81
Description INTERRUPT STATUS REGISTER TO MCU. IRQ0 STATUS LINE.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVF_IRQ
CSI2A_IRQ CSI2C_IRQ
RESERVED RESERVED RESERVED RESERVED RESERVED
HS_VS_IRQ CBUFF_IRQ
CSIB_LC3_IRQ CSIB_LC2_IRQ CSIB_LC1_IRQ CSIB_LC0_IRQ OCP_ERR_IRQ
CSIB_LCM_IRQ
MMU_ERR_IRQ
CCDC_VD2_IRQ CCDC_VD1_IRQ CCDC_VD0_IRQ RSZ_DONE_IRQ PRV_DONE_IRQ
CCDC_ERR_IRQ
HIST_DONE_IRQ
CCDC_LSC_DONE
H3A_AF_DONE_IRQ
H3A_AWB_DONE_IRQ
CCDC_LSC_PREFETCH_ERROR
CCDC_LSC_PREFETCH_COMPLETED
Bits Field Name Description Type Reset
31 HS_VS_IRQ HS or VS synchro event
(1)
R/W/1to 0
READS: Clr
0: Event is false
1: Event is true
WRITES
0: Status bit unchanged
1: Status bit reset
30 RESERVED Write 0s for future compatibility. Read returns 0. RW 0
29 OCP_ERR_IRQ ISP interconnect error. R/W/1to 0
READS: Clr
0: Event is false
1: Event is true
WRITES
0: Status bit unchanged
1: Status bit reset
28 MMU_ERR_IRQ MMU error. R/W/1to 0
If event is true, one needs to read the MMU_IRQSTATUS register Clr
to know the event source. Write in MMU_IRQSTATUS to clear the
bit.
READS:
0: Event is false
1: Event is true
27:26 RESERVED Write 0s for future compatibility. Read returns 0. R/W/1to 0
Clr
25 OVF_IRQ Central Resource SBL overflow R/W/1to 0
If event is true, one needs to check the SBL_PCR register to know Clr
the source. One needs to clear the SBL_PCR register first before
clearing this bit.
READS:
0: Event is false
1: Event is true
WRITES
0: Status bit unchanged
1: Status bit reset
(1)
This event is detected on the incoming HS/VS signals before the CCDC. Therefore, it cannot be used in BT656 mode.
1308 Camera Image Signal Processor SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated