Texas Instruments OMAP36 Series, Technical Reference Manual

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PRCM Register Manual
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Table 3-140. CM_FCLKEN3_CORE
Address Offset 0x0000 0008
Physical Address 0x4800 4A08 Instance CORE_CM
Description Controls the module functional clock activity.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
EN_TS
RESERVED
EN_USBTLL
Bits Field Name Description Type Reset
31:3 RESERVED Write 0s for future compatibility. Read returns 0. R 0x00000000
2 EN_USBTLL USB TLL functional clock control. RW 0x0
0x0: USB TLL functional clock is disabled
0x1: USB TLL functional clock is enabled
1 EN_TS Temperature Sensors functional clock control. RW 0x0
0x0: Temperature Sensors functional clock is disabled
(for both BandGap)
0x1: Temperature Sensors functional clock is enabled
(for both BandGap)
0 RESERVED Reserved for non-GP devices. RW 0x0
Table 3-141. Register Call Summary for Register CM_FCLKEN3_CORE
PRCM Functional Description
• CM Source-Clock Controls : [0]
• CORE Power Domain Clock Controls : [1] [2]
PRCM Basic Programming Model
• CM_FCLKEN_ <domain_name> (Functional Clock Enable Register) : [3]
PRCM Register Manual
• CORE_CM Register Summary : [4]
Table 3-142. CM_ICLKEN1_CORE
Address Offset 0x0000 0010
Physical Address 0x4800 4A10 Instance CORE_CM
Description Controls the modules interface clock activity.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN_ICR
EN_I2C3 EN_I2C2 EN_I2C1
EN_HDQ
EN_SDRC EN_MMC3 EN_MMC2 EN_MMC1
EN_GPT11 EN_GPT10
EN_UART2 EN_UART1
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
EN_MCSPI4 EN_MCSPI3 EN_MCSPI2 EN_MCSPI1
EN_MCBSP5 EN_MCBSP1
EN_HSOTGUSB
EN_MAILBOXES
EN_OMAPCTRL
476 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010
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