Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 343 / 3738

SYS_CLK EFUSE_ALWON_FCLK
HC
Source selection/division Software control Hardware control
prcm-064
Public Version
www.ti.com
PRCM Functional Description
Table 3-50. CORE Power Domain Clock-Gating Controls (continued)
Clock Name Reset Clock-Gating Control Gating Description
CORE_L3_ICLK Running PRCM. CM_ICLKEN1_CORE Gated when:
EN_(SDRC, HSOTGUSB),
• All enable bits are set to 0.
PRCM. CM_AUTOIDLE1_CORE 4]
• The enable-autoidle bit pair is set to 1,
AUTO_HSOTGUSB
the remaining enable bits are set to 0,
and the clock is not requested by any
module.
CORE_L4_ICLK Running PRCM. CM_ICLKEN1_CORE Gated when:
(MMC[1..2], HDQ, MCSPI[1-4],
• All enable bits are set to 0.
I2C[1-3], UART[1,2], GPT[10,11],
• All enable-autoidle bit pairs are set to
MCBSP[1,5], MAILBOXES,
1, and the clock is not requested by
OMAPCTRL )
any module.
and PRCM. CM_AUTOIDLE1_CORE
(MMC[1..2], HDQ, MCSPI[1-4],
I2C[1-3], UART[1,2], GPT[10,11],
MCBSP[1,5], MAILBOXES,
OMAPCTRL
)
CORE_32K_FCLK Stopped CM_FCLKEN1_CORE [24] EN_MMC1, Gated when all enable bits are set to 0
CM_FCLKEN1_CORE [25] EN_MMC2,
CM_FCLKEN1_CORE [30] EN_MMC3,
CM_FCLKEN3_CORE [1] EN_TS
USBTLL_SAR_FCLK Stopped CORE power domain power state and Gated when the save-restore bit is set to 0,
PM_PWSTCTRL_CORE [4] or when the CORE power domain is in off
SAVEANDRESTORE state after the save operation completes or
in on state after the restore operation
completes
CORE_120M_FCLK Stopped CM_FCLKEN3_CORE [0] EN_USBTLL Gated when the enable bit is set to 0, or
and DPLL5 operating mode the DPLL5 is in stop or bypass mode
3.5.3.7.7 EFUSE Power Domain Clock Controls
Figure 3-67 shows the clock controls for the EFUSE power domain. Table 3-51 lists the clock-gating
control for the EFUSE power domain.
Figure 3-67. EFUSE Power Domain Clock Controls
Table 3-51. EFUSE Power Domain Clock-Gating Control
Clock Name Reset Clock-Gating Control Gating Description
EFUSE_ALWON_FCLK Running None Active when VDD1 and VDD2 are switched
on and eFuse-ready hardware signal is
released
3.5.3.7.8 DSS Power Domain Clock Controls
This section describes all modules and features in the high-tier device. To save power, ensure that power
domains of unavailable features and modules are switched off and clocks are cut off.
Figure 3-68 shows the clock controls for the DSS power domain. Table 3-52 lists the clock-gating controls
for the DSS power domain.
343 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management
Copyright © 2009–2010, Texas Instruments Incorporated