MPU INTC
ARM host processor (Step 4)
If FIQs are enabled(F==0):
Finish the current instruction number N
Store address of next instruction to be executed in the
Link Register (R14)
Save CPSR before execution in the SPSR
Enter ARM FIQ mode
Execute interrupt vector
Device peripheral module
M_IRQ_n
asserted
MPU _INTC_IRQ/
MPU _INTC_FIQ
asserted
Save ARM critical context
Identify interrupt source
Branch to revelant interrupt subroutine handler
Handles the event (functional procedure)
Deassert the interrupt M_IRQ_n at device
Allow a new IRQ/FIQ at INTC side by setting the
NEWIRQAGR/NEWFIQAGR bit to 1.
Restore ARM critical context
Branch
ARM host processor (Step 8)
Restore the whole CPSR
Restore the PC
Branch
Branch
Return
intc-005
Main Program
Software
Execution of the instruction number 1
Execution of the instruction number N
Hardware
Step 1
Step 2
Main program
Execution of the instruction number N+1
Return
peripheral
module side.
If the IRQ_n is not masked and configured as an IRQ/FIQ,
the MPU_INTC_IRQ/MPU_INT_FIQ line is asserted
ISR in IRQ/FIQ mode (Step 5)
Revelant subroutine handler in IRQ/FIQ mode (Step 6)
Disable IRQs and FIQs at ARM side
ISR in IRQ/FIQ mode (Step 7)
Public Version
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Interrupt Controller Basic Programming Model
Figure 12-5. IRQ/FIQ Processing Sequence
NOTE:
The differences between the IRQ and the FIQ sequence are highlighted in blue and bold
characters.
The priority sorting mechanism is frozen during an interrupt processing sequence. If an
interrupt condition occurs during this time, the interrupt is not lost. It is sorted when the
NEWIRQAGR/NEWFIQAGR bit is set (priority sorting is reactivated).
2417
SWPU177N – December 2009 – Revised November 2010
Interrupt Controller
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